Specification	CDCE72010RGCR

Differential - Input:Output [custom]	True
Differential - Input:Output [custom]	True
Divider/Multiplier	Yes/No
Frequency - Max [Max]	1.5 GHz
Input	LVDS, LVCMOS, LVPECL
Mounting Type	Surface Mount
Number of Circuits	1
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output	LVDS, LVPECL, LVCMOS
Package / Case	64-VFQFN Exposed Pad
PLL	True
Ratio - Input:Output [custom]	3:20
Supplier Device Package	64-VQFN (9x9)
Type	Fanout (Distribution), Jitter Cleaner, Clock Synchronizer
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	3 V

CDCE72010 Series

10 outputs low jitter clock synchronizer and jitter cleaner

Part	Input	Voltage - Supply [Max]	Voltage - Supply [Min]	Frequency - Max [Max]	Divider/Multiplier	Operating Temperature [Max]	Operating Temperature [Min]	Type	Number of Circuits	Mounting Type	Output	Ratio - Input:Output [custom]	Supplier Device Package	Package / Case	Utilized IC / Part	Supplied Contents	Contents	Function
Texas Instruments CDCE72010RGCR	LVCMOS LVDS LVPECL	3.6 V	3 V	1.5 GHz	Yes/No	85 °C	-40 °C	Clock Synchronizer Fanout (Distribution) Jitter Cleaner	1	Surface Mount	LVCMOS LVDS LVPECL	3:20	64-VQFN (9x9)	64-VFQFN Exposed Pad
Texas Instruments CDCE72010EVM								Timing							CDCE72010	Board(s)	Board(s)	Clock Generator
Texas Instruments CDCE72010RGCT	LVCMOS LVDS LVPECL	3.6 V	3 V	1.5 GHz	Yes/No	85 °C	-40 °C	Clock Synchronizer Fanout (Distribution) Jitter Cleaner	1	Surface Mount	LVCMOS LVDS LVPECL	3:20	64-VQFN (9x9)	64-VFQFN Exposed Pad

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tape & Reel (TR)	2000	$ 11.20
Texas Instruments	LARGE T&R	1	$ 14.38
		100	$ 12.56
		250	$ 9.69
		1000	$ 8.66

Description

General part information

CDCE72010 Series

The CDCE72010 is a high-performance, low phase noise, and low skew clock synchronizer that synchronizes a VCXO (Voltage Controlled Crystal Oscillator) or VCO (Voltage Controlled Oscillator) frequency to one of two reference clocks. The clock path is fully programmable providing the user with a high degree of flexibility. The following relationship applies to the dividers:

Frequency (VCXO_IN or AUX_IN) / Frequency (PRI_REF or SEC_REF) = (P*N)/(R*M)

The VC(X)O_IN clock operates up to 1.5GHz through the selection of external VC(X)O and loop filter components. The PLL loop bandwidth and damping factor can be adjusted to meet different system requirements.