CDCE72010 Series

10 outputs low jitter clock synchronizer and jitter cleaner

Catalog

10 outputs low jitter clock synchronizer and jitter cleaner

Part	Input	Voltage - Supply [Max]	Voltage - Supply [Min]	Frequency - Max [Max]	Divider/Multiplier	Operating Temperature [Max]	Operating Temperature [Min]	Type	Number of Circuits	Mounting Type	Output	Ratio - Input:Output [custom]	Supplier Device Package	Package / Case	Utilized IC / Part	Supplied Contents	Contents	Function
Texas Instruments CDCE72010RGCR	LVCMOS LVDS LVPECL	3.6 V	3 V	1.5 GHz	Yes/No	85 °C	-40 °C	Clock Synchronizer Fanout (Distribution) Jitter Cleaner	1	Surface Mount	LVCMOS LVDS LVPECL	3:20	64-VQFN (9x9)	64-VFQFN Exposed Pad
Texas Instruments CDCE72010EVM								Timing							CDCE72010	Board(s)	Board(s)	Clock Generator
Texas Instruments CDCE72010RGCT	LVCMOS LVDS LVPECL	3.6 V	3 V	1.5 GHz	Yes/No	85 °C	-40 °C	Clock Synchronizer Fanout (Distribution) Jitter Cleaner	1	Surface Mount	LVCMOS LVDS LVPECL	3:20	64-VQFN (9x9)	64-VFQFN Exposed Pad

Catalog

10 outputs low jitter clock synchronizer and jitter cleaner

Key Features

• High Performance LVPECL, LVDS, LVCMOS PLL Clock SynchronizerTwo Reference Clock Inputs (Primary and Secondary Clock) for RedundancySupport with Manual or Automatic SelectionAccepts Two Differential Input (LVPECL or LVDS) References up to 500MHz(or Two LVCMOS Inputs up to 250MHz) as PLL ReferenceVCXO_IN Clock is Synchronized to One of Two Reference ClocksVCXO_IN Frequencies up to 1.5GHz (LVPECL)800MHz for LVDS and250MHz for LVCMOS Level SignalingOutputs Can be a Combination of LVPECL, LVDS, and LVCMOS(Up to 10 Differential LVPECL or LVDS Outputs or up to20 LVCMOS Outputs), Output 9 can be Converted to anAuxiliary Input as a 2nd VC(X)O.Output Divider is Selectable to Divide by 1, 2, 3, 4, 5, 6, 8, 10,12, 16, 18, 20, 24, 28, 30, 32, 36, 40, 42, 48, 50, 56, 60, 64, 70,or 80 On Each Output Individually up to Eight Dividers. (Except forOutput 0 and 9, Output 0 Follows Output 1 Divider and Output 9Follows Output 8 Divider)SPI Controllable Device SettingIndividual Output Enable Control via SPI InterfaceIntegrated On-Chip Non-Volatile Memory (EEPROM) to Store Settingswithout the Need to Apply High Voltage to the DeviceOptional Configuration Pins to Select Between Two Default SettingsStored in EEPROMEfficient Jitter Cleaning from Low PLL Loop BandwidthVery Low Phase Noise PLL CoreProgrammable Phase Offset (Input Reference to Outputs)Wide Charge-Pump Current Range From 200µA to 3mAPresets Charge-Pump to VCC_CP/2 for Fast Center-FrequencySetting of VC(X)O, Controlled Via the SPI BusSERDES Startup Mode (Depending on VCXO Range)Auxiliary Input: Output 9 can Serve as 2nd VCXO Input to DriveAll Outputs or to Serve as PLL Feedback SignalRESETorHOLDInput Pin to Serve as Reset or Hold FunctionsREFERENCE SELECT for Manual Select Between Primary and SecondaryReference ClocksPOWER DOWN (PD) to Put Device in Standby ModeAnalog and Digital PLL Lock IndicatorInternally Generated VBB Bias Voltages for Single-Ended Input SignalsFrequency Hold-Over Mode Activated byHOLDPin or SPI Bus to ImproveFail-Safe OperationInput to All Outputs Skew ControlIndividual Skew Control for Each Output with Each Output DividerPackaged in a QFN-64 PackageESD Protection Exceeds 2kV HBMIndustrial Temperature Range of –40°C to 85°High Performance LVPECL, LVDS, LVCMOS PLL Clock SynchronizerTwo Reference Clock Inputs (Primary and Secondary Clock) for RedundancySupport with Manual or Automatic SelectionAccepts Two Differential Input (LVPECL or LVDS) References up to 500MHz(or Two LVCMOS Inputs up to 250MHz) as PLL ReferenceVCXO_IN Clock is Synchronized to One of Two Reference ClocksVCXO_IN Frequencies up to 1.5GHz (LVPECL)800MHz for LVDS and250MHz for LVCMOS Level SignalingOutputs Can be a Combination of LVPECL, LVDS, and LVCMOS(Up to 10 Differential LVPECL or LVDS Outputs or up to20 LVCMOS Outputs), Output 9 can be Converted to anAuxiliary Input as a 2nd VC(X)O.Output Divider is Selectable to Divide by 1, 2, 3, 4, 5, 6, 8, 10,12, 16, 18, 20, 24, 28, 30, 32, 36, 40, 42, 48, 50, 56, 60, 64, 70,or 80 On Each Output Individually up to Eight Dividers. (Except forOutput 0 and 9, Output 0 Follows Output 1 Divider and Output 9Follows Output 8 Divider)SPI Controllable Device SettingIndividual Output Enable Control via SPI InterfaceIntegrated On-Chip Non-Volatile Memory (EEPROM) to Store Settingswithout the Need to Apply High Voltage to the DeviceOptional Configuration Pins to Select Between Two Default SettingsStored in EEPROMEfficient Jitter Cleaning from Low PLL Loop BandwidthVery Low Phase Noise PLL CoreProgrammable Phase Offset (Input Reference to Outputs)Wide Charge-Pump Current Range From 200µA to 3mAPresets Charge-Pump to VCC_CP/2 for Fast Center-FrequencySetting of VC(X)O, Controlled Via the SPI BusSERDES Startup Mode (Depending on VCXO Range)Auxiliary Input: Output 9 can Serve as 2nd VCXO Input to DriveAll Outputs or to Serve as PLL Feedback SignalRESETorHOLDInput Pin to Serve as Reset or Hold FunctionsREFERENCE SELECT for Manual Select Between Primary and SecondaryReference ClocksPOWER DOWN (PD) to Put Device in Standby ModeAnalog and Digital PLL Lock IndicatorInternally Generated VBB Bias Voltages for Single-Ended Input SignalsFrequency Hold-Over Mode Activated byHOLDPin or SPI Bus to ImproveFail-Safe OperationInput to All Outputs Skew ControlIndividual Skew Control for Each Output with Each Output DividerPackaged in a QFN-64 PackageESD Protection Exceeds 2kV HBMIndustrial Temperature Range of –40°C to 85°

Description

The CDCE72010 is a high-performance, low phase noise, and low skew clock synchronizer that synchronizes a VCXO (Voltage Controlled Crystal Oscillator) or VCO (Voltage Controlled Oscillator) frequency to one of two reference clocks. The clock path is fully programmable providing the user with a high degree of flexibility. The following relationship applies to the dividers: Frequency (VCXO_IN or AUX_IN) / Frequency (PRI_REF or SEC_REF) = (P*N)/(R*M) The VC(X)O_IN clock operates up to 1.5GHz through the selection of external VC(X)O and loop filter components. The PLL loop bandwidth and damping factor can be adjusted to meet different system requirements. The CDCE72010 can lock to one of two reference clock inputs (PRI_REF and SEC_REF) and supports frequency hold-over mode for fail-safe and system redundancy. The outputs of the CDCE72010 are user definable and can be any combination of up to 10 LVPECL/LVDS outputs or up to 20 LVCMOS outputs. The built-in synchronization latches ensure that all outputs are synchronized for very low output skew. All device settings, including output signaling, divider value selection, input selection, and many more, are programmable with the SPI (4-wire Serial Peripheral Interface). The SPI allows individual control of the device settings. The device operates in a 3.3V environment and is characterized for operation from –40°C to +85°C. The CDCE72010 is available in a 64-pin lead-free "green" plastic quad flatpack package with enhanced bottom thermal pad for heat dissipation. The Texas Instruments package designator is RGC (S-PQFP-N64). The CDCE72010 is a high-performance, low phase noise, and low skew clock synchronizer that synchronizes a VCXO (Voltage Controlled Crystal Oscillator) or VCO (Voltage Controlled Oscillator) frequency to one of two reference clocks. The clock path is fully programmable providing the user with a high degree of flexibility. The following relationship applies to the dividers: Frequency (VCXO_IN or AUX_IN) / Frequency (PRI_REF or SEC_REF) = (P*N)/(R*M) The VC(X)O_IN clock operates up to 1.5GHz through the selection of external VC(X)O and loop filter components. The PLL loop bandwidth and damping factor can be adjusted to meet different system requirements. The CDCE72010 can lock to one of two reference clock inputs (PRI_REF and SEC_REF) and supports frequency hold-over mode for fail-safe and system redundancy. The outputs of the CDCE72010 are user definable and can be any combination of up to 10 LVPECL/LVDS outputs or up to 20 LVCMOS outputs. The built-in synchronization latches ensure that all outputs are synchronized for very low output skew. All device settings, including output signaling, divider value selection, input selection, and many more, are programmable with the SPI (4-wire Serial Peripheral Interface). The SPI allows individual control of the device settings. The device operates in a 3.3V environment and is characterized for operation from –40°C to +85°C. The CDCE72010 is available in a 64-pin lead-free "green" plastic quad flatpack package with enhanced bottom thermal pad for heat dissipation. The Texas Instruments package designator is RGC (S-PQFP-N64).