Technical Specifications
Parameters and characteristics for this part
| Specification | FDG6322C |
|---|---|
| Configuration | N and P-Channel |
| Current - Continuous Drain (Id) @ 25°C | 410 mA, 220 mA |
| Drain to Source Voltage (Vdss) | 25 V |
| FET Feature | Logic Level Gate |
| Gate Charge (Qg) (Max) @ Vgs | 0.4 nC |
| Input Capacitance (Ciss) (Max) @ Vds | 9.5 pF |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 150 °C |
| Operating Temperature [Min] | -55 °C |
| Package / Case | 6-TSSOP, SC-88, SOT-363 |
| Power - Max [Max] | 300 mW |
| Rds On (Max) @ Id, Vgs | 4 Ohm |
| Supplier Device Package | SC-88 (SC-70-6) |
| Technology | MOSFET (Metal Oxide) |
| Vgs(th) (Max) @ Id | 1.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
Description
General part information
FDG6322C Series
These dual N & P-Channel logic level enhancement mode field effect transistors are produced using a proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs. Since bias resistors are not required, this dual digital FET can replace several different digital transistors, with different bias resistor values.
Documents
Technical documentation and resources