FDG6322C Series

Dual N & P Channel Digital FET 25V

Catalog

Dual N & P Channel Digital FET 25V

Part	Power - Max [Max]	Current - Continuous Drain (Id) @ 25°C	Drain to Source Voltage (Vdss)	Gate Charge (Qg) (Max) @ Vgs	FET Feature	Vgs(th) (Max) @ Id	Operating Temperature [Min]	Operating Temperature [Max]	Supplier Device Package	Configuration	Mounting Type	Input Capacitance (Ciss) (Max) @ Vds	Package / Case	Rds On (Max) @ Id, Vgs	Technology
ON Semiconductor FDG6322C	300 mW	220 mA 410 mA	25 V	0.4 nC	Logic Level Gate	1.5 V	-55 °C	150 °C	SC-88 (SC-70-6)	N and P-Channel	Surface Mount	9.5 pF	6-TSSOP SC-88 SOT-363	4 Ohm	MOSFET (Metal Oxide)

Catalog

Dual N & P Channel Digital FET 25V

Key Features

• N-Ch 0.22 A, 25 V,RDS(ON)= 4.0 Ω @ VGS= 4.5 V,RDS(ON)= 5.0 Ω @ VGS= 2.7 V

• P-Ch -0.41 A,-25V,RDS(ON)= 1.1 Ω @ VGS= -4.5V,RDS(ON)= 1.5 Ω @ VGS= -2.7V.

• Very small package outline SC70-6.

• Very low level gate drive requirements allowing direct operation in 3 V circuits (VGS(th)< 1.5 V)

• Gate-Source Zener for ESD ruggedness (>6k V Human Body Model).

Description

These dual N & P-Channel logic level enhancement mode field effect transistors are produced using a proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs. Since bias resistors are not required, this dual digital FET can replace several different digital transistors, with different bias resistor values.