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Texas Instruments-TPS2010DRG4 Power Switches Power Switch Hi Side 1-OUT 0A 140mOhm 8-Pin SOIC T/R
Integrated Circuits (ICs)

TPS7301QD

Active
Texas Instruments

500-MA, 10-V, LOW-DROPOUT VOLTAGE REGULATOR WITH POWER GOOD & ENABLE

Texas Instruments-TPS2010DRG4 Power Switches Power Switch Hi Side 1-OUT 0A 140mOhm 8-Pin SOIC T/R
Integrated Circuits (ICs)

TPS7301QD

Active
Texas Instruments

500-MA, 10-V, LOW-DROPOUT VOLTAGE REGULATOR WITH POWER GOOD & ENABLE

Technical Specifications

Parameters and characteristics for this part

SpecificationTPS7301QD
Control FeaturesEnable
Current - Output500 mA
Current - Supply (Max) [Max]550 µA
Mounting TypeSurface Mount
Number of Regulators1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Output ConfigurationPositive
Output TypeAdjustable
Package / Case8-SOIC
Package / Case [x]0.154 in
Package / Case [y]3.9 mm
Protection FeaturesOver Temperature, Over Current, Under Voltage Lockout (UVLO), Reverse Polarity
PSRR68 dB
Supplier Device Package8-SOIC
Voltage - Input (Max) [Max]10 V
Voltage - Output (Max) [Max]9.75 V
Voltage - Output (Min/Fixed)1.2 V
Voltage Dropout (Max) [Max]0.21 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
ArrowN/A 75$ 3.06
DigikeyTube 1$ 4.95
Texas InstrumentsTUBE 1$ 4.25
100$ 3.73
250$ 2.61
1000$ 2.10

Description

General part information

TPS7301 Series

The TPS73xx devices are members of a family of micropower low-dropout (LDO) voltage regulators. They are differentiated from the TPS71xx and TPS72xx LDOs by their integrated delayed microprocessor-reset function. If the precision delayed reset is not required, the TPS71xx and TPS72xx should be considered.

The RESET\ output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.

If that occurs, the RESET\ output (open-drain NMOS) turns on, taking the RESET\ signal low. RESET\ stays low for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-out begins. At the completion of the 200-ms delay, RESET\ goes high.