SN74F573DWR
ActiveOCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
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SN74F573DWR
ActiveOCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
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Technical Specifications
Parameters and characteristics for this part
| Specification | SN74F573DWR |
|---|---|
| Circuit [custom] | 8 |
| Circuit [custom] | 8 |
| Current - Output High, Low [custom] | 3 mA |
| Current - Output High, Low [custom] | 24 mA |
| Delay Time - Propagation | 8.6 ns |
| Independent Circuits | 1 |
| Logic Type | D-Type Transparent Latch |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Output Type | Tri-State |
| Package / Case | 20-SOIC |
| Package / Case [y] | 0.295 in |
| Package / Case [y] | 7.5 mm |
| Supplier Device Package | 20-SOIC |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 0.75 | |
| 10 | $ 0.54 | |||
| 25 | $ 0.48 | |||
| 100 | $ 0.42 | |||
| 250 | $ 0.39 | |||
| 500 | $ 0.38 | |||
| 1000 | $ 0.37 | |||
| Digi-Reel® | 1 | $ 0.75 | ||
| 10 | $ 0.54 | |||
| 25 | $ 0.48 | |||
| 100 | $ 0.42 | |||
| 250 | $ 0.39 | |||
| 500 | $ 0.38 | |||
| 1000 | $ 0.37 | |||
| Tape & Reel (TR) | 2000 | $ 0.35 | ||
| 4000 | $ 0.34 | |||
| 6000 | $ 0.34 | |||
| 10000 | $ 0.33 | |||
| 14000 | $ 0.33 | |||
| 20000 | $ 0.33 | |||
| Texas Instruments | LARGE T&R | 1 | $ 0.60 | |
| 100 | $ 0.46 | |||
| 250 | $ 0.34 | |||
| 1000 | $ 0.24 | |||
Description
General part information
SN74F573 Series
These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches of the ´F573 are transparent D-type latches. While the latch enable (LE) input is high, the Q outputs follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
A buffered output enableinput can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high- impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
Documents
Technical documentation and resources