Specification	SN74F573DW

Circuit [custom]	8
Circuit [custom]	8
Current - Output High, Low [custom]	3 mA
Current - Output High, Low [custom]	24 mA
Delay Time - Propagation	8.6 ns
Independent Circuits	1
Logic Type	D-Type Transparent Latch
Mounting Type	Surface Mount
Operating Temperature [Max]	70 °C
Operating Temperature [Min]	0 °C
Output Type	Tri-State
Package / Case	20-SOIC
Package / Case [y]	0.295 in
Package / Case [y]	7.5 mm
Supplier Device Package	20-SOIC
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	4.5 V

SN74F573 Series

Octal Transparent D-Type Latches With 3-State Outputs

Part	Supplier Device Package	Mounting Type	Independent Circuits	Operating Temperature [Max]	Operating Temperature [Min]	Voltage - Supply [Min]	Voltage - Supply [Max]	Delay Time - Propagation	Output Type	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Circuit [custom]	Circuit [custom]	Package / Case	Package / Case [y]	Package / Case [y]	Logic Type
Texas Instruments SN74F573DWR	20-SOIC	Surface Mount	1	70 °C	0 °C	4.5 V	5.5 V	8.6 ns	Tri-State	3 mA	24 mA	8	8	20-SOIC	0.295 in	7.5 mm	D-Type Transparent Latch
Texas Instruments SN74F573DW	20-SOIC	Surface Mount	1	70 °C	0 °C	4.5 V	5.5 V	8.6 ns	Tri-State	3 mA	24 mA	8	8	20-SOIC	0.295 in	7.5 mm	D-Type Transparent Latch

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tube	1	$ 1.00
		10	$ 0.89
		25	$ 0.85
		100	$ 0.70
		250	$ 0.65
		500	$ 0.58
Texas Instruments	TUBE	1	$ 0.74
		100	$ 0.57
		250	$ 0.42
		1000	$ 0.30

Description

General part information

SN74F573 Series

These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the ´F573 are transparent D-type latches. While the latch enable (LE) input is high, the Q outputs follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

A buffered output enableinput can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high- impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

Documents

Technical documentation and resources

Octal Transparent D-Type Latches With 3-State Outputs datasheet (Rev. A)

Data sheet