Specification	CLVC2G126MDCUTEP

Current - Output High, Low [x]	32 mA
Current - Output High, Low [y]	32 mA
Logic Type	Buffer, Non-Inverting
Mounting Type	Surface Mount
Number of Bits per Element	1
Number of Elements	2
Operating Temperature [Max]	125 ¯C
Operating Temperature [Min]	-55 °C
Output Type	3-State
Package / Case	8-VFSOP
Package / Case [y]	2.3 mm
Package / Case [y]	0.091 in
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	1.65 V

SN74LVC2G126-EP Series

Enhanced product 2-ch, 1.65-V to 5.5-V buffers with 3-state outputs

Part	Logic Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Package / Case [y]	Package / Case	Package / Case [y]	Output Type	Operating Temperature [Max]	Operating Temperature [Min]	Number of Bits per Element	Mounting Type	Number of Elements	Current - Output High, Low [y]	Current - Output High, Low [x]
Texas Instruments CLVC2G126MDCUTEP	Buffer Non-Inverting	5.5 V	1.65 V	2.3 mm	8-VFSOP	0.091 in	3-State	125 ¯C	-55 °C	1	Surface Mount	2	32 mA	32 mA

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 3.02
		10	$ 2.72
		25	$ 2.57
		100	$ 2.23
	Digi-Reel®	1	$ 3.02
		10	$ 2.72
		25	$ 2.57
		100	$ 2.23
	Tape & Reel (TR)	250	$ 2.11
		500	$ 1.89
		1250	$ 1.60
		2500	$ 1.52
		6250	$ 1.46
Texas Instruments	SMALL T&R	1	$ 2.63
		100	$ 2.30
		250	$ 1.61
		1000	$ 1.30

Description

General part information

SN74LVC2G126-EP Series

This dual bus buffer gate is designed for 1.65-V to 5.5-V VCCoperation.

The SN74LVC2G126 is a dual bus driver/line driver with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

Documents

Technical documentation and resources

Little Logic Guide 2018 (Rev. G)

Selection guide

Use of the CMOS Unbuffered Inverter in Oscillator Circuits

Application note

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Application note

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Application note

Implications of Slow or Floating CMOS Inputs (Rev. E)

Application note

CLVC2G126MDCUTEP

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CLVC2G126MDCUTEP

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Technical Specifications

SN74LVC2G126-EP Series

Pricing

Description

SN74LVC2G126-EP Series

Documents

Little Logic Guide 2018 (Rev. G)

Use of the CMOS Unbuffered Inverter in Oscillator Circuits

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Live Insertion

LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)

LOGIC Pocket Data Book (Rev. B)

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Low-Voltage Logic (LVC) Designer's Guide

STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS

Logic Guide (Rev. AB)

Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices

Standard Linear & Logic for PCs, Servers & Motherboards

CMOS Power Consumption and CPD Calculation (Rev. B)

Dual Bus Buffer Gate With 3-State Outputs, SN74LVC2G126-EP datasheet

Signal Switch Data Book (Rev. A)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Selecting the Right Level Translation Solution (Rev. A)

Texas Instruments Little Logic Application Report

TI IBIS File Creation, Validation, and Distribution Processes

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

LVC Characterization Information

Input and Output Characteristics of Digital Integrated Circuits

How to Select Little Logic (Rev. A)

Design Summary for WCSP Little Logic (Rev. B)

Understanding Advanced Bus-Interface Products Design Guide

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Implications of Slow or Floating CMOS Inputs (Rev. E)

SN74LVC2G126-EP Series