LMK00725PW
ActiveLOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3-V LVPECL FANOUT BUFFER
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LMK00725PW
ActiveLOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3-V LVPECL FANOUT BUFFER
Technical Specifications
Parameters and characteristics for this part
| Specification | LMK00725PW |
|---|---|
| Differential - Input:Output [custom] | True |
| Differential - Input:Output [custom] | True |
| Frequency - Max [Max] | 650 MHz |
| Input | HCSL, LVPECL, SSTL, LVDS, LVHSTL |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output | LVPECL |
| Package / Case | 20-TSSOP |
| Package / Case [x] | 0.173 in |
| Package / Case [y] | 4.4 mm |
| Ratio - Input:Output | 2:5 |
| Supplier Device Package | 20-TSSOP |
| Type | Fanout Buffer (Distribution), Multiplexer |
| Voltage - Supply [Max] | 3.465 V |
| Voltage - Supply [Min] | 3.135 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 1 | $ 6.56 | |
| 10 | $ 5.92 | |||
| 73 | $ 5.65 | |||
| 146 | $ 4.90 | |||
| 292 | $ 4.85 | |||
| Texas Instruments | TUBE | 1 | $ 7.14 | |
| 100 | $ 5.82 | |||
| 250 | $ 4.58 | |||
| 1000 | $ 3.88 | |||
Description
General part information
LMK00725 Series
The LMK00725 is a low skew, high-performance clock fanout buffer which can distribute up to five 3.3V LVPECL outputs from one of two inputs, which can accept differential or single-ended inputs. The clock enable input is synchronized internally to eliminate runt or glitch pulses on the outputs when the clock enable pin is asserted or de-asserted. The low additive jitter and phase noise floor and ensured output and part-to-part skew characteristics make the LMK00725 ideal for applications demanding high performance and repeatability.
The LMK00725 is a low skew, high-performance clock fanout buffer which can distribute up to five 3.3V LVPECL outputs from one of two inputs, which can accept differential or single-ended inputs. The clock enable input is synchronized internally to eliminate runt or glitch pulses on the outputs when the clock enable pin is asserted or de-asserted. The low additive jitter and phase noise floor and ensured output and part-to-part skew characteristics make the LMK00725 ideal for applications demanding high performance and repeatability.
Documents
Technical documentation and resources