LMK00725 Series

Low skew, 1-to-5, differential-to-3.3-V LVPECL fanout buffer

Catalog

Low skew, 1-to-5, differential-to-3.3-V LVPECL fanout buffer

Part	Operating Temperature [Max]	Operating Temperature [Min]	Package / Case [y]	Package / Case	Package / Case [x]	Output	Supplier Device Package	Ratio - Input:Output	Differential - Input:Output [custom]	Differential - Input:Output [custom]	Frequency - Max [Max]	Input	Mounting Type	Number of Circuits	Type	Voltage - Supply [Max]	Voltage - Supply [Min]
Texas Instruments LMK00725PW	85 °C	-40 °C	4.4 mm	20-TSSOP	0.173 in	LVPECL	20-TSSOP	2:5			650 MHz	HCSL LVDS LVHSTL LVPECL SSTL	Surface Mount	1	Fanout Buffer (Distribution) Multiplexer	3.465 V	3.135 V

Catalog

Low skew, 1-to-5, differential-to-3.3-V LVPECL fanout buffer

Key Features

• Five 3.3V Differential LVPECL OutputsAdditive Jitter: 43 fs RMS (typ) @ 312.5 MHzNoise Floor (≥1 MHz offset):–158 dBc/Hz (typ) @ 312.5 MHzOutput Frequency: 650 MHz (max)Output Skew: 35 ps (max)Part-to-Part Skew: 100 ps (max)Propagation Delay: 0.37 ns (max)Two Differential Input Pairs (pin-selectable)CLKx, nCLK Input Pairs can accept LVPECL,LVDS, HCSL, SSTL, LVHSTL, or Single-EndedSignalsSynchronous Clock EnablePower Supply: 3.3V ±5%Package: 20-Lead TSSOPIndustrial Temperature Range: –40°C to +85°CFive 3.3V Differential LVPECL OutputsAdditive Jitter: 43 fs RMS (typ) @ 312.5 MHzNoise Floor (≥1 MHz offset):–158 dBc/Hz (typ) @ 312.5 MHzOutput Frequency: 650 MHz (max)Output Skew: 35 ps (max)Part-to-Part Skew: 100 ps (max)Propagation Delay: 0.37 ns (max)Two Differential Input Pairs (pin-selectable)CLKx, nCLK Input Pairs can accept LVPECL,LVDS, HCSL, SSTL, LVHSTL, or Single-EndedSignalsSynchronous Clock EnablePower Supply: 3.3V ±5%Package: 20-Lead TSSOPIndustrial Temperature Range: –40°C to +85°C

Description

The LMK00725 is a low skew, high-performance clock fanout buffer which can distribute up to five 3.3V LVPECL outputs from one of two inputs, which can accept differential or single-ended inputs. The clock enable input is synchronized internally to eliminate runt or glitch pulses on the outputs when the clock enable pin is asserted or de-asserted. The low additive jitter and phase noise floor and ensured output and part-to-part skew characteristics make the LMK00725 ideal for applications demanding high performance and repeatability. The LMK00725 is a low skew, high-performance clock fanout buffer which can distribute up to five 3.3V LVPECL outputs from one of two inputs, which can accept differential or single-ended inputs. The clock enable input is synchronized internally to eliminate runt or glitch pulses on the outputs when the clock enable pin is asserted or de-asserted. The low additive jitter and phase noise floor and ensured output and part-to-part skew characteristics make the LMK00725 ideal for applications demanding high performance and repeatability.