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Integrated Circuits (ICs)

SN74LVC374AQPWREP

Active
Texas Instruments

ENHANCED PRODUCT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

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20-pin (PW) package image
Integrated Circuits (ICs)

SN74LVC374AQPWREP

Active
Texas Instruments

ENHANCED PRODUCT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74LVC374AQPWREP
Clock Frequency100 MHz
Current - Output High, Low24 mA
Current - Quiescent (Iq)10 µA
FunctionStandard
Input Capacitance4 pF
Max Propagation Delay @ V, Max CL8.5 ns
Mounting TypeSurface Mount
Number of Bits per Element8
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Output TypeTri-State, Non-Inverted
Package / Case20-TSSOP
Package / Case [x]0.173 in
Package / Case [y]4.4 mm
Supplier Device Package20-TSSOP
Trigger TypePositive Edge
TypeD-Type
Voltage - Supply [Max]3.6 V
Voltage - Supply [Min]2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 2.28
Digi-Reel® 1$ 2.28
Tape & Reel (TR) 2000$ 1.04
6000$ 1.00
10000$ 0.97
Texas InstrumentsLARGE T&R 1$ 1.71
100$ 1.42
250$ 1.02
1000$ 0.77

Description

General part information

SN74LVC374A-EP Series

The SN74LVC374A-EP octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCCoperation.

This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.

Documents

Technical documentation and resources

Selecting the Right Level Translation Solution (Rev. A)

Application note

LOGIC Pocket Data Book (Rev. B)

User guide

Use of the CMOS Unbuffered Inverter in Oscillator Circuits

Application note

TI IBIS File Creation, Validation, and Distribution Processes

Application note

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

Application note

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Application note

How to Select Little Logic (Rev. A)

Application note

Design Summary for WCSP Little Logic (Rev. B)

Product overview

LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)

User guide

Standard Linear & Logic for PCs, Servers & Motherboards

More literature

Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices

Application note

Little Logic Guide 2018 (Rev. G)

Selection guide

Texas Instruments Little Logic Application Report

Application note

STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS

More literature

Power-Up Behavior of Clocked Devices (Rev. B)

Application note

Logic Guide (Rev. AB)

Selection guide

Input and Output Characteristics of Digital Integrated Circuits

Application note

SN74LVC374A-EP datasheet (Rev. A)

Data sheet

CMOS Power Consumption and CPD Calculation (Rev. B)

Application note

Signal Switch Data Book (Rev. A)

User guide

Live Insertion

Application note

Understanding Advanced Bus-Interface Products Design Guide

Application note

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Application note

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Application note

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Application note

Implications of Slow or Floating CMOS Inputs (Rev. E)

Application note

LVC Characterization Information

Application note

Low-Voltage Logic (LVC) Designer's Guide

Design guide