
SN74LVC374ADWR
ActiveFLIP FLOP D-TYPE BUS INTERFACE POS-EDGE 3-ST 1-ELEMENT 20-PIN SOIC T/R
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SN74LVC374ADWR
ActiveFLIP FLOP D-TYPE BUS INTERFACE POS-EDGE 3-ST 1-ELEMENT 20-PIN SOIC T/R
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74LVC374ADWR |
|---|---|
| Clock Frequency | 100 MHz |
| Current - Output High, Low | 24 mA |
| Current - Quiescent (Iq) | 10 µA |
| Function | Standard |
| Input Capacitance | 4 pF |
| Max Propagation Delay @ V, Max CL | 7 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 8 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Tri-State, Non-Inverted |
| Package / Case | 20-SOIC |
| Package / Case [y] | 0.295 in |
| Package / Case [y] | 7.5 mm |
| Supplier Device Package | 20-SOIC |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 1.65 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 0.73 | |
| 10 | $ 0.64 | |||
| 25 | $ 0.60 | |||
| 100 | $ 0.49 | |||
| 250 | $ 0.46 | |||
| 500 | $ 0.39 | |||
| 1000 | $ 0.31 | |||
| Digi-Reel® | 1 | $ 0.73 | ||
| 10 | $ 0.64 | |||
| 25 | $ 0.60 | |||
| 100 | $ 0.49 | |||
| 250 | $ 0.46 | |||
| 500 | $ 0.39 | |||
| 1000 | $ 0.31 | |||
| Tape & Reel (TR) | 2000 | $ 0.25 | ||
| 6000 | $ 0.23 | |||
| 10000 | $ 0.23 | |||
| Texas Instruments | LARGE T&R | 1 | $ 0.42 | |
| 100 | $ 0.33 | |||
| 250 | $ 0.24 | |||
| 1000 | $ 0.17 | |||
Description
General part information
SN74LVC374A-EP Series
The SN74LVC374A-EP octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCCoperation.
This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.
Documents
Technical documentation and resources