The AD9554-1 is a low loop bandwidth clock translator that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9554-1 generates an output clock synchronized to up to four external input references. The digital PLLs (DPLLs) allow reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9554-1 continuously generates a low jitter output clock even when all reference inputs have failed.The AD9554-1 operates over an industrial temperature range of −40°C to +85°C. The AD9554 is a version of this device with two outputs per PLL. If a single or dual DPLL version of this device is needed, refer to theAD9557orAD9559, respectively.ApplicationsNetwork synchronization, including synchronous Ethernet and synchronous digital hierarchy (SDH) to optical transport network (OTN) mapping/demappingCleanup of reference clock jitterSONET/SDH clocks up to OC-192, including FECStratum 3 holdover, jitter cleanup, and phase transient controlCable infrastructureData communicationsProfessional video