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32-LFCSP-VQ
Integrated Circuits (ICs)

ADAU1381BCPZ

Obsolete
Analog Devices

LOW-NOISE STEREO CODEC WITH ENHANCED RECORDING AND PLAYBACK PROCESSING

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32-LFCSP-VQ
Integrated Circuits (ICs)

ADAU1381BCPZ

Obsolete
Analog Devices

LOW-NOISE STEREO CODEC WITH ENHANCED RECORDING AND PLAYBACK PROCESSING

Technical Specifications

Parameters and characteristics for this part

SpecificationADAU1381BCPZ
Data InterfaceSPI
Dynamic Range, ADCs / DACs (db) Typ [custom]100 db
Dynamic Range, ADCs / DACs (db) Typ [custom]96.5 db
Mounting TypeSurface Mount
Number of ADCs / DACs [custom]2
Number of ADCs / DACs [custom]2
Operating Temperature [Max]85 °C
Operating Temperature [Min]-25 °C
Package / Case32-VFQFN Exposed Pad, CSP
Resolution (Bits)24 b
S/N Ratio, ADCs / DACs (db) Typ [custom]97 db
S/N Ratio, ADCs / DACs (db) Typ [custom]100 db
Sigma DeltaFalse
Supplier Device Package32-LFCSP-VQ (5x5)
TypeStereo Audio
Voltage - Supply, Analog [Max]3.65 V
Voltage - Supply, Analog [Min]1.8 V
Voltage - Supply, Digital [Max]3.65 V
Voltage - Supply, Digital [Min]1.63 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

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Description

General part information

ADAU1381 Series

The ADAU1381 is a low-power, 24-bit stereo audio codec. The stereo audio DAC supports sample rates from 8 kHz to 96 kHz, a digital volume control, and a programmable digital filter. The stereo audio ADC supports sample rates 8 kHz to 96 kHz and a programmable digital volume control. The ADAU1381 is ideal for battery-powered audio applications.The record path includes two digital stereo microphone inputs and an analog stereo input path. The analog inputs can be configured for either a pseudo-differential or a single-ended stereo source. Additionally, there is a dedicated analog beep input signal path that can be mixed into any output. The ADAU1381 includes a stereo line output and speaker driver, which makes the device capable of supporting dynamic speakers.The serial control bus supports the I2C or SPI protocols, and the serial audio bus is programmable for I2S, left-justified, right-justified, or TDM mode. A programmable PLL supports flexible clock generation for all standard rates and available master clocks from 8 MHz to 27 MHz.ApplicationsDigital still camerasDigital video cameras