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Technical Specifications
Parameters and characteristics for this part
| Specification | SY10EP51VKG-TR |
|---|---|
| Clock Frequency | 3 GHz |
| Current - Quiescent (Iq) | 40 mA |
| Function | Reset |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 1 bits |
| Number of Elements | 1 |
| Operating Temperature (Max) | 85 °C |
| Operating Temperature (Min) | -40 °C |
| Output Type | Complementary |
| Package Length | 0.118 in |
| Package Name | 8-MSOP, 8-TSSOP, 8-MSOP |
| Package Width | 3 mm |
| Trigger Type | Positive, Negative |
| Type | D-Type |
| Voltage - Supply (Maximum) | -3 V |
| Voltage - Supply (Minimum) | -5.5 V |
| Part | Mounting Type | Package Name | Voltage - Supply (Minimum) | Voltage - Supply (Maximum) | Operating Temperature (Max) | Operating Temperature (Min) | Trigger Type | Number of Elements | Output Type | Clock Frequency | Type | Function | Package Length | Package Width | Current - Quiescent (Iq) | Number of Bits per Element | Package / Case |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
 Microchip Technology | Surface Mount | 8-SOIC | -5.5 V | -3 V | 85 °C | -40 °C | Negative Positive | 1 | Complementary | 3 GHz | D-Type | Reset | 0.154 in | 3.9 mm | 40 mA | 1 bits | |
 Microchip Technology | Surface Mount | 8-MSOP 8-TSSOP 8-MSOP | -5.5 V | -3 V | 85 °C | -40 °C | Negative Positive | 1 | Complementary | 3 GHz | D-Type | Reset | 0.118 in | 3 mm | 40 mA | 1 bits | |
Microchip Technology | Surface Mount | 8-MSOP 8-TSSOP 8-MSOP | -5.5 V | -3 V | 70 °C | 0 °C | Negative Positive | 1 | Complementary | 3 GHz | D-Type | Reset | 0.118 in | 3 mm | 40 mA | 1 bits | |
Microchip Technology | Surface Mount | 8-SOIC | -5.5 V | -3 V | 85 °C | -40 °C | Negative Positive | 1 | Complementary | 3 GHz | D-Type | Reset | 0.154 in | 3.9 mm | 40 mA | 1 bits | |
 Microchip Technology | Surface Mount | 8-MLF® | -5.5 V | -3 V | 85 °C | -40 °C | Negative Positive | 1 | Complementary | 3 GHz | D-Type | Reset | 2 mm | 2 mm | 40 mA | 1 bits | 8-MLF® 8-VFDFN Exposed Pad |
Microchip Technology | Surface Mount | 8-SOIC | -5.5 V | -3 V | 70 °C | 0 °C | Negative Positive | 1 | Complementary | 3 GHz | D-Type | Reset | 0.154 in | 3.9 mm | 40 mA | 1 bits | |
Microchip Technology | Surface Mount | 8-SOIC | -5.5 V | -3 V | 70 °C | 0 °C | Negative Positive | 1 | Complementary | 3 GHz | D-Type | Reset | 0.154 in | 3.9 mm | 40 mA | 1 bits | |
Microchip Technology | Surface Mount | 8-MSOP 8-TSSOP 8-MSOP | -5.5 V | -3 V | 70 °C | 0 °C | Negative Positive | 1 | Complementary | 3 GHz | D-Type | Reset | 0.118 in | 3 mm | 40 mA | 1 bits | |
 Microchip Technology | Surface Mount | 8-SOIC | -5.5 V | -3 V | 85 °C | -40 °C | Negative Positive | 1 | Complementary | 3 GHz | D-Type | Reset | 0.154 in | 3.9 mm | 40 mA | 1 bits | |
Microchip Technology | Surface Mount | 8-MSOP 8-TSSOP 8-MSOP | -5.5 V | -3 V | 85 °C | -40 °C | Negative Positive | 1 | Complementary | 3 GHz | D-Type | Reset | 0.118 in | 3 mm | 40 mA | 1 bits |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | Updated |
|---|---|---|---|---|
| Digikey | Tape & Reel (TR) | 1000 | $ 3.04 | <2d |
| Microchip Direct | T/R | 1 | $ 3.77 | 1m+ |
| 25 | $ 3.14 | |||
| 100 | $ 2.86 | |||
| 1000 | $ 2.76 | |||
| 5000 | $ 2.73 | |||
| 10000 | $ 2.70 | |||
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Description
General part information
10EP51 Series
The SY10EP51V is a D flip-flop with reset and differential clock. The device is pin and functionally equivalent to the EL51 device.The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when CLK is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the CLK. The differential clock inputs of the EP51V allow the device to be used as a negative edge triggered flip-flop.The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to VEE and the /CLK input will be biased a VCC/2.
Documents
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