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Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | PL123-09SC |
|---|---|
| Differential - Input:Output | False |
| Divider/Multiplier | False |
| Frequency - Max [Max] | 134 MHz |
| Input | Clock |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Output | Clock |
| Package / Case | 16-SOIC |
| Package / Case [x] | 0.154 in |
| Package / Case [y] | 3.9 mm |
| PLL | Yes with Bypass |
| Ratio - Input:Output | 1:9 |
| Supplier Device Package | 16-SOP |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 1 | $ 5.94 | |
| Microchip Direct | TUBE | 1 | $ 5.94 | |
| 25 | $ 4.95 | |||
| 100 | $ 4.50 | |||
| 1000 | $ 3.74 | |||
| 5000 | $ 3.47 | |||
| 10000 | $ 3.22 | |||
Description
General part information
PL123E-05 Series
The PL123-05/-09 (-05H/-09H for High Drive) are high performance, low skew, low jitter zero delay buffers designed to distribute high speed clocks. They have one (PL123-05) or two (PL123-09) low-skew output banks, of 4 outputs each, that are synchronized with the input. The PL123-09 allows control of the banks of outputs by using the S1 and S2 inputs as shown in the Selector Definition table on page 2 of the datasheet.The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than ±100ps, the device acts as a zero delay buffer. The input output propagation delay can be advanced or delayed by adjusting the load on the CLKOUT pin.These parts are not intended for 5V input-tolerant applications.
Documents
Technical documentation and resources