
Deep-Dive with AI
Search across all available documentation for this part.

Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | SY87701VHC |
|---|---|
| Differential - Input:Output [custom] | True |
| Differential - Input:Output [custom] | True |
| Frequency - Max [Max] | 1.25 Gbps |
| Input | TTL, PECL |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | 0 °C |
| Output | PECL |
| Package / Case | 32-TQFP Exposed Pad |
| PLL | True |
| Ratio - Input:Output [custom] | 3:3 |
| Supplier Device Package | 32-TQFP-EP |
| Supplier Device Package [custom] | 7x7 |
| Voltage - Supply [Max] | 5.25 V |
| Voltage - Supply [Min] | 3.15 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
SY87701A Series
The SY87701AL is a complete Clock Recovery and Data Retiming integrated circuit for data rates from 28Mbps up to 1.3Gbps NRZ. The device is ideally suited for SONET/SDH/ATM and Fibre Channel applications and other high-speed data transmission systems. Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the incoming data stream. The VCO center frequency is controlled by the reference clock frequency and the selected divide ratio. On-chip clock generation is performed through the use of a frequency multiplier PLL with a byte rate source as reference. The SY87701AL also includes a link fault detection circuit.
Documents
Technical documentation and resources