STM32G473MBT6
ActiveMAINSTREAM ARM CORTEX-M4 MCU 170 MHZ WITH 128 KBYTES OF FLASH MEMORY, MATH ACCELERATOR, HIGH ANALOG LEVEL INTEGRATION
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STM32G473MBT6
ActiveMAINSTREAM ARM CORTEX-M4 MCU 170 MHZ WITH 128 KBYTES OF FLASH MEMORY, MATH ACCELERATOR, HIGH ANALOG LEVEL INTEGRATION
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Technical Specifications
Parameters and characteristics for this part
| Specification | STM32G473MBT6 |
|---|---|
| Connectivity | QSPI, UART/USART, USB, CANbus, I2C, SPI, SAI, IrDA, LINbus |
| Core Processor | ARM® Cortex®-M4 |
| Core Size | 32-Bit |
| Data Converters | 41, 7 |
| Data Converters | 12b |
| Mounting Type | Surface Mount |
| Number of I/O | 66 |
| Operating Temperature [Max] | 85 C |
| Operating Temperature [Min] | -40 ¯C |
| Oscillator Type | External, Internal |
| Package / Case | 80-LQFP |
| Peripherals | PWM, Brown-out Detect/Reset, I2S, TRNG, WDT, DMA, POR |
| Program Memory Size | 128 KB |
| Program Memory Type | FLASH |
| RAM Size | 128 K |
| Speed | 170 MHz |
| Voltage - Supply (Vcc/Vdd) [Max] | 3.6 V |
| Voltage - Supply (Vcc/Vdd) [Min] | 1.71 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | N/A | 0 | $ 4.14 | |
Description
General part information
STM32G473MB Series
The STM32G473xB/xC/xE devices are based on the high-performance Arm®Cortex®-M4 32-bit RISC core. They operate at a frequency of up to 170 MHz.
The Cortex-M4 core features a single-precision floating-point unit (FPU), which supports all the Arm single-precision data-processing instructions and all the data types. It also implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) which enhances the application’s security.
These devices embed high-speed memories (up to 512 Kbytes of flash memory, and 128 Kbytes of SRAM), a flexible external memory controller (FSMC) for static memories (for devices with packages of 100 pins and more), a Quad-SPI flash memory interface, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.
Documents
Technical documentation and resources
