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56-TFSOP (0.240", 6.10mm Width)
Integrated Circuits (ICs)

DS90C383BMT/NOPB

Active
Texas Instruments

+3.3V PROGRAMMABLE LVDS TRANSMITTER 24-BIT FLAT PANEL DISPLAY (FPD) LINK-65 MHZ

56-TFSOP (0.240", 6.10mm Width)
Integrated Circuits (ICs)

DS90C383BMT/NOPB

Active
Texas Instruments

+3.3V PROGRAMMABLE LVDS TRANSMITTER 24-BIT FLAT PANEL DISPLAY (FPD) LINK-65 MHZ

Technical Specifications

Parameters and characteristics for this part

SpecificationDS90C383BMT/NOPB
Data Rate1.8 Gbps
Mounting TypeSurface Mount
Number of Drivers/Receivers [custom]5
Number of Drivers/Receivers [custom]0
Operating Temperature [Max] [custom]158 °F
Operating Temperature [Min] [custom]-10 °C
Package / Case6.1 mm
Package / Case0.24 in
Package / Case56-TFSOP
ProtocolLVDS, FPD-Link
Supplier Device Package56-TSSOP
TypeDriver
Voltage - Supply [Max]3.6 V
Voltage - Supply [Min]3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyBulk 97$ 3.11
Tube 1$ 4.05
10$ 3.64
34$ 3.44
102$ 2.98
272$ 2.83
510$ 2.69
Texas InstrumentsTUBE 1$ 4.35
100$ 3.81
250$ 2.67
1000$ 2.15

Description

General part information

DS90C383B Series

The DS90C383 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CF384 receiver converts the LVDS data streams back into 28 bits of CMOS/TTL data. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughputs is 227 Mbytes/sec. The transmitter is offered with programmable edge data strobes for convenient interface with a variety of graphics controllers. The transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge transmitter will inter-operate with a Falling edge receiver (DS90CF384) without any translation logic. The DS90CF384 is also offered in 64 ball, 0.8mm fine pitch ball grid array(FBGA) package which provides a 44 % reduction in PCB footprint (available Q3, 1999).

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

The DS90C383 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CF384 receiver converts the LVDS data streams back into 28 bits of CMOS/TTL data. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughputs is 227 Mbytes/sec. The transmitter is offered with programmable edge data strobes for convenient interface with a variety of graphics controllers. The transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge transmitter will inter-operate with a Falling edge receiver (DS90CF384) without any translation logic. The DS90CF384 is also offered in 64 ball, 0.8mm fine pitch ball grid array(FBGA) package which provides a 44 % reduction in PCB footprint (available Q3, 1999).