Zenode.ai Logo
Beta
SPC560D40L3B4E0X
Integrated Circuits (ICs)

SPC560D40L3B4E0X

Active
STMicroelectronics

32-BIT POWER ARCHITECTURE MCU FOR AUTOMOTIVE BODY AND GATEWAY APPLICATIONS

Deep-Dive with AI

Search across all available documentation for this part.

SPC560D40L3B4E0X
Integrated Circuits (ICs)

SPC560D40L3B4E0X

Active
STMicroelectronics

32-BIT POWER ARCHITECTURE MCU FOR AUTOMOTIVE BODY AND GATEWAY APPLICATIONS

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationSPC560D40L3B4E0X
ConnectivityCANbus, LINbus, UART/USART, SPI
Core Processore200z0h
Core Size32-Bit
Data ConvertersA/D 33x12b
GradeAutomotive
Mounting TypeSurface Mount
Number of I/O79 I/O
Operating Temperature [Max]105 °C
Operating Temperature [Min]-40 °C
Oscillator TypeInternal
Package / Case100-LQFP
PeripheralsPOR, LVD, PWM, WDT, DMA
Program Memory Size256 KB
Program Memory TypeFLASH
QualificationAEC-Q100
RAM Size16 K
Speed48 MHz
Supplier Device Package100-LQFP (14x14)
Voltage - Supply (Vcc/Vdd) [Max]5.5 V
Voltage - Supply (Vcc/Vdd) [Min]3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyN/A 0$ 3.48

Description

General part information

SPC560D40L3 Series

These 32-bit automotive microcontrollers are a family of system-on-chip (SoC) devices designed to be central to the development of the next wave of central vehicle body controller, smart junction box, front module, peripheral body, door control and seat control applications.

This family is one of a series of next-generation integrated automotive microcontrollers based on the Power Architecture technology and designed specifically for embedded applications.

The advanced and cost-efficient e200z0h host processor core of this automotive controller family complies with the Power Architecture technology and only implements the VLE (variable-length encoding) APU (auxiliary processing unit) and provides improved code density. It operates at speed of up to 48 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current power architecture devices and is supported with software drivers, operating systems and configuration code to assist with the user’s implementations.