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LQFP / 48
Integrated Circuits (ICs)

HV2733FG-G

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Microchip Technology

16-CH LOW HARMONIC DISTORTION, HIGH VOLTAGE ANALOG SWITCH W/BLEED RESISTORS 48 LQFP 7X7X1.4MM TRAY ROHS COMPLIANT: YES

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LQFP / 48
Integrated Circuits (ICs)

HV2733FG-G

Active
Microchip Technology

16-CH LOW HARMONIC DISTORTION, HIGH VOLTAGE ANALOG SWITCH W/BLEED RESISTORS 48 LQFP 7X7X1.4MM TRAY ROHS COMPLIANT: YES

Technical Specifications

Parameters and characteristics for this part

SpecificationHV2733FG-G
-3db Bandwidth50 MHz
ApplicationsUltrasound
Mounting TypeSurface Mount
Multiplexer/Demultiplexer Circuit1:1
Number of Channels16
On-State Resistance (Max) [Max]38 Ohm
Operating Temperature [Max]70 °C
Operating Temperature [Min]0 °C
Package / Case48-LQFP
Supplier Device Package48-LQFP (7x7)
Switch CircuitSPST
Voltage - Supply, Dual (V±) [Max]160 V
Voltage - Supply, Dual (V±) [Min]-40 V
Voltage - Supply, Single (V+) [Max]200 V
Voltage - Supply, Single (V+) [Min]40 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTray 1$ 38.35
25$ 31.98
100$ 29.07
Microchip DirectTRAY 1$ 38.35
25$ 31.98
100$ 29.07
1000$ 28.07
5000$ 27.75
NewarkEach 100$ 29.95

Description

General part information

HV2733 Series

HV2733 is a low charge injection, 16-channel, low harmonic distortion, high voltage analog switch integrated circuit (IC) intended for use in applications requiring high voltage switching, controlled by low voltage control signals, such as medical ultrasound imaging, piezoelectric transducer drivers, and printers. The bleed resistors eliminate voltage built up on capacitive loads such as piezoelectric transducers.

The outputs are configured as single-pole double-throw analog switches. Data are shifted into a 8-bit shift register using an external clock. The LE latches the shift register data into the individual switch latches. A logic high connects a switch common YX to SWX. A logic low connects YX to SWX. A logic high in CLR resets all switches to SWX simultaneously.

To reduce any possible clock feed-through noise, the latch enable bar (LE) should be left high until all bits are clocked in. Data are clocked in during the rising edge of the clock. Using HVCMOS technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals.