DS90UR907Q-EVK/NOPB
ObsoleteDS90UR907Q LVDS EVALUATION KIT AUTOMOTIVE AEC-Q100
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DS90UR907Q-EVK/NOPB
ObsoleteDS90UR907Q LVDS EVALUATION KIT AUTOMOTIVE AEC-Q100
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Technical Specifications
Parameters and characteristics for this part
| Specification | DS90UR907Q-EVK/NOPB |
|---|---|
| Function | Serializer |
| Supplied Contents | Board(s) |
| Type | Interface |
| Utilized IC / Part | DS90UR907Q |
DS90UR907Q-Q1 Series
5 - 65 MHz 24-bit Color FPD-Link to FPD-Link II Converter
| Part | Grade | Output Type | Package / Case | Operating Temperature [Max] | Operating Temperature [Min] | Mounting Type | Voltage - Supply [Max] | Voltage - Supply [Min] | Qualification | Number of Outputs | Supplier Device Package | Function | Data Rate | Number of Inputs | Type | Supplied Contents | Utilized IC / Part |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
 Texas Instruments | Automotive | FPD-Link II LVDS | 36-WFQFN Exposed Pad | 105 °C | -40 °C | Surface Mount | 1.89 V 3.6 V | 1.71 V 3 V | AEC-Q100 | 1 | 36-WQFN (6x6) | Serializer | 1.82 Gbps | 5 | |||
Texas Instruments | Serializer | Interface | Board(s) | DS90UR907Q | |||||||||||||
Texas Instruments | Automotive | FPD-Link II LVDS | 36-WFQFN Exposed Pad | 105 °C | -40 °C | Surface Mount | 1.89 V 3.6 V | 1.71 V 3 V | AEC-Q100 | 1 | 36-WQFN (6x6) | Serializer | 1.82 Gbps | 5 | |||
Texas Instruments | Automotive | FPD-Link II LVDS | 36-WFQFN Exposed Pad | 105 °C | -40 °C | Surface Mount | 1.89 V 3.6 V | 1.71 V 3 V | AEC-Q100 | 1 | 36-WQFN (6x6) | Serializer | 1.82 Gbps | 5 |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
DS90UR907Q-Q1 Series
The DS90UR907Q-Q1 converts FPD-Link to FPD-Link II. It translates four LVDS data/control streams and one LVDS clock pair (FPD-Link) into a high-speed serialized interface (FPD-Link II) over a single pair. This serial bus scheme greatly eases system design by eliminating skew problems between clock and data, reduces the number of connector pins, reduces the interconnect size, weight, and cost, and overall eases PCB layout. In addition, internal DC balanced encoding is used to support AC-coupled interconnects.
The DS90UR907Q-Q1 converts, balances and level shifts four LVDS data/control streams, and embeds one LVDS clock pair (FPD-Link) to a serial stream (FPD-Link II). Up to 24 bits of RGB in the FPD-Link are serialized along with the three video control signals.
Serial transmission is optimized by a user selectable de-emphasis and differential output level select features. EMI is minimized by the use of low voltage differential signaling and spread spectrum clocking compatibility.
Documents
Technical documentation and resources