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Technical Specifications
Parameters and characteristics for this part
| Specification | CDCVF25081PW |
|---|---|
| Differential - Input:Output | False |
| Divider/Multiplier | False |
| Frequency - Max [Max] | 200 MHz |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output | LVTTL |
| Package / Case | 16-TSSOP |
| Package / Case [x] | 0.173 in |
| Package / Case [y] | 4.4 mm |
| PLL | Yes with Bypass |
| Ratio - Input:Output [custom] | 8 |
| Ratio - Input:Output [custom] | 2 |
| Supplier Device Package | 16-TSSOP |
| Type | PLL Clock Driver |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 1 | $ 3.02 | |
| 10 | $ 2.71 | |||
| 90 | $ 2.22 | |||
| 270 | $ 2.11 | |||
| 540 | $ 2.01 | |||
| Texas Instruments | TUBE | 1 | $ 3.24 | |
| 100 | $ 2.84 | |||
| 250 | $ 1.99 | |||
| 1000 | $ 1.61 | |||
Description
General part information
CDCVF25081 Series
The CDCVF25081 is a high performance, low skew, low jitter, phased-locked loop clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks to the input clock signal. The outputs are divided into 2 banks for a total of 8 buffered CLKIN outputs. The device automatically puts the outputs to a low state when no CLKIN signal is present (power down mode).
The S1 and S2 pins allow selection between PLL or bypassed PLL outputs. When left open, the outputs are disabled to a logic low state.
The part supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.
Documents
Technical documentation and resources
