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8-TDFN 3x3
Integrated Circuits (ICs)

HIP2103FRTAAZ

Active
Renesas Electronics Corporation

MOTOR DRIVER/CONTROLLER, THREE PHASE DC BRUSHLESS, 4.5V TO 14V SUPPLY, 75 MA/1 OUTPUT, TDFN-8

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8-TDFN 3x3
Integrated Circuits (ICs)

HIP2103FRTAAZ

Active
Renesas Electronics Corporation

MOTOR DRIVER/CONTROLLER, THREE PHASE DC BRUSHLESS, 4.5V TO 14V SUPPLY, 75 MA/1 OUTPUT, TDFN-8

Deep-Dive with AI

DocumentsDatasheet

Technical Specifications

Parameters and characteristics for this part

SpecificationHIP2103FRTAAZ
Channel TypeIndependent
Current - Peak Output (Source, Sink) [custom]1 A
Current - Peak Output (Source, Sink) [custom]1 A
Driven ConfigurationHalf-Bridge
Gate TypeN-Channel MOSFET
Input TypeNon-Inverting
Logic Voltage - VIL, VIH1.63 V, 2.06 V
Mounting TypeSurface Mount
Number of Drivers2
Operating Temperature [Max]125 ¯C
Operating Temperature [Min]-40 °C
Package / Case8-WDFN Exposed Pad
Supplier Device Package8-TDFN (3x3)
Voltage - Supply [Max]14 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 2.59
10$ 2.33
25$ 2.20
100$ 1.87
250$ 1.76
500$ 1.54
1000$ 1.27
3000$ 1.19
5000$ 1.14

Description

General part information

HIP2103 Series

The HIP2103 is a half-bridge driver designed for applications using DC motors, 3-phase brushless DC motors, or other similar loads. The two inputs (HI and LI) independently control the high-side driver (HO) and the low-side driver (LO). HI and LI can be configured to enable/disable the device, which lowers the number of connections to a microcontroller and the cost. The low IDDbias current in the Sleep mode prevents battery drain when the device is not in use, which eliminates the need for an external switch to disconnect the driver from the battery. Integrated pull-down resistors on all of the inputs (LI, HI, VDen, and VCen) reduce the need for external resistors. An active-low resistance pull-down on the LO output ensures that the low-side bridge FET remains off during the Sleep mode or when VDDis below the Undervoltage Lockout (UVLO) threshold.

Documents

Technical documentation and resources