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Technical Specifications
Parameters and characteristics for this part
| Specification | NLV14042BDR2G |
|---|---|
| Circuit | 1:1 |
| Current - Output High, Low [custom] | 8.8 mA |
| Current - Output High, Low [custom] | 8.8 mA |
| Delay Time - Propagation | 60 ns |
| Independent Circuits | 4 |
| Logic Type | D-Type Transparent Latch |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Output Type | Differential |
| Package / Case | 16-SOIC |
| Package / Case [x] | 0.154 in |
| Package / Case [y] | 3.9 mm |
| Supplier Device Package | 16-SOIC |
| Voltage - Supply [Max] | 18 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 1.04 | |
| 10 | $ 0.61 | |||
| 25 | $ 0.51 | |||
| 100 | $ 0.39 | |||
| 250 | $ 0.34 | |||
| 500 | $ 0.31 | |||
| 1000 | $ 0.28 | |||
| Digi-Reel® | 1 | $ 1.04 | ||
| 10 | $ 0.61 | |||
| 25 | $ 0.51 | |||
| 100 | $ 0.39 | |||
| 250 | $ 0.34 | |||
| 500 | $ 0.31 | |||
| 1000 | $ 0.28 | |||
| Tape & Reel (TR) | 2500 | $ 0.20 | ||
| Newark | Each (Supplied on Full Reel) | 1 | $ 0.27 | |
| 3000 | $ 0.27 | |||
| 6000 | $ 0.25 | |||
| 12000 | $ 0.23 | |||
| 18000 | $ 0.21 | |||
| 30000 | $ 0.20 | |||
| ON Semiconductor | N/A | 1 | $ 0.21 | |
Description
General part information
MC14042B Series
The MC14042B Quad Transparent Latch is constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. Each latch has a separate data input, but all four latches share a common clock. The clock polarity (high or low) used to strobe data through the latches can be reversed using the polarity input. Information present at the data input is transferred to outputs Q and Q during the clock level which is determined by the polarity input. When the polarity input is in the logic "0" state, data is transferred during the low clock level, and when the polarity input is in the logic "1" state the transfer occurs during the high clock level.
Documents
Technical documentation and resources