MC14042B Series

Quad Transparent Latch

Catalog

Quad Transparent Latch

Part	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Package / Case	Package / Case [x]	Package / Case [y]	Logic Type	Independent Circuits	Delay Time - Propagation	Output Type	Supplier Device Package	Voltage - Supply [Max]	Voltage - Supply [Min]	Operating Temperature [Min]	Operating Temperature [Max]	Mounting Type	Circuit	Package / Case	Package / Case
ON Semiconductor NLV14042BDG	8.8 mA	8.8 mA	16-SOIC	0.154 in	3.9 mm	D-Type Transparent Latch	4	60 ns	Differential	16-SOIC	18 V	3 V	-55 °C	125 °C	Surface Mount	1:1
ON Semiconductor MC14042BDG	8.8 mA	8.8 mA	16-SOIC	0.154 in	3.9 mm	D-Type Transparent Latch	4	60 ns	Differential	16-SOIC	18 V	3 V	-55 °C	125 °C	Surface Mount	1:1
ON Semiconductor NLV14042BDR2G	8.8 mA	8.8 mA	16-SOIC	0.154 in	3.9 mm	D-Type Transparent Latch	4	60 ns	Differential	16-SOIC	18 V	3 V	-55 °C	125 °C	Surface Mount	1:1
ON Semiconductor MC14042BCPG	8.8 mA	8.8 mA	16-DIP			D-Type Transparent Latch	4	60 ns	Differential	16-PDIP	18 V	3 V	-55 °C	125 °C	Through Hole	1:1	0.3 in	7.62 mm
ON Semiconductor MC14042BDR2	8.8 mA	8.8 mA	16-SOIC	0.154 in	3.9 mm	D-Type Transparent Latch	4	60 ns	Differential	16-SOIC	18 V	3 V	-55 °C	125 °C	Surface Mount	1:1
ON Semiconductor MC14042BDR2G	8.8 mA	8.8 mA	16-SOIC	0.154 in	3.9 mm	D-Type Transparent Latch	4	60 ns	Differential	16-SOIC	18 V	3 V	-55 °C	125 °C	Surface Mount	1:1
ON Semiconductor MC14042BD	8.8 mA	8.8 mA	16-SOIC	0.154 in	3.9 mm	D-Type Transparent Latch	4	60 ns	Differential	16-SOIC	18 V	3 V	-55 °C	125 °C	Surface Mount	1:1

Catalog

Quad Transparent Latch

Key Features

• Buffered Data Inputs

• Common Clock

• Clock Polarity Control

• Q and Qbar Outputs

• Double Diode Input Protection

• Supply Voltage Range = 3.0 Vdc to 1 8 Vdc

• Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range

• Pb-Free Packages are Available*

Description

The MC14042B Quad Transparent Latch is constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. Each latch has a separate data input, but all four latches share a common clock. The clock polarity (high or low) used to strobe data through the latches can be reversed using the polarity input. Information present at the data input is transferred to outputs Q and Q during the clock level which is determined by the polarity input. When the polarity input is in the logic "0" state, data is transferred during the low clock level, and when the polarity input is in the logic "1" state the transfer occurs during the high clock level.