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Development Boards, Kits, Programmers

ISL6548A-6506EVAL1Z

Obsolete
Renesas Electronics Corporation

EVALUATION BOARD ISL6548A-6506

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Development Boards, Kits, Programmers

ISL6548A-6506EVAL1Z

Obsolete
Renesas Electronics Corporation

EVALUATION BOARD ISL6548A-6506

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationISL6548A-6506EVAL1Z
Board TypeFully Populated
Current - Output10 A, 2 A, 14 A, 5 A, 15 A
Main PurposeSpecial Purpose DC/DC, DDR Memory Supply
Outputs and TypeNon-Isolated
Outputs and Type7
Power - Output178 W
Regulator TopologyBuck
Supplied ContentsBoard(s)
Utilized IC / PartISL6506, ISL6548A
Voltage - Input12 VDC, 3.3 V, 5 VDC
Voltage - Output2.5 V, 5 V, 0.9 V, 1.2 V, 1.5 V, 1.8 V, 3.3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

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Description

General part information

ISL6548A Series

The ISL6548A provides a complete ACPI compliant power solution for up to 4 DIMM dual channel DDR/DDR2 Memory systems. Included are both a synchronous buck controller to supply VDDQduring S0/S1 and S3 states. During S0/S1 state, a fully integrated sink-source regulator generates an accurate (VDDQ/2) high current VTTvoltage without the need for a negative supply. A second PWM controller, which requires external MOSFET drivers, is available for regulation of the GMCH Core voltage. A sink/source LDO controller is also integrated for the CPU/GMCH VTTtermination voltage regulation. Another LDO is available for the ICH7 voltage. The switching PWM controller drives two N-Channel MOSFETs in a synchronous-rectified buck converter topology. The synchronous buck converter uses voltage-mode control with fast transient response. The switching regulator provides a maximum static regulation tolerance of ±2% over line, load, and temperature ranges. The output is user-adjustable by means of external resistors down to 0. 8V. An integrated soft-start feature brings all outputs into regulation in a controlled manner when returning to S0/S1 state from any sleep state. During S0 the VIDPGD signal indicates that the GMCH and CPU VTTtermination voltage is within spec and operational. All outputs, except VICH7, have undervoltage protection. The switching regulator also has overvoltage and overcurrent protection. Thermal shutdown is integrated.

Documents

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