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TSSOP (PW)
Integrated Circuits (ICs)

CD4098BPW

Obsolete
Texas Instruments

MONOSTABLE MULTIVIBRATOR DUAL-ELEMENT -55°C 125°C 16-PIN TSSOP TUBE

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Search across all available documentation for this part.

DocumentsCD4098B Types datasheet (Rev. C)Logic Guide (Rev. AB)+6
TSSOP (PW)
Integrated Circuits (ICs)

CD4098BPW

Obsolete
Texas Instruments

MONOSTABLE MULTIVIBRATOR DUAL-ELEMENT -55°C 125°C 16-PIN TSSOP TUBE

Deep-Dive with AI

DocumentsCD4098B Types datasheet (Rev. C)Logic Guide (Rev. AB)+6

Technical Specifications

Parameters and characteristics for this part

SpecificationCD4098BPW
Current - Output High, Low [custom]6.8 mA
Current - Output High, Low [custom]6.8 mA
Independent Circuits2
Logic TypeMonostable
Mounting TypeSurface Mount
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Package / Case16-TSSOP
Package / Case [x]0.173 in
Package / Case [y]4.4 mm
Propagation Delay100 ns
Schmitt Trigger InputFalse
Supplier Device Package16-TSSOP
Voltage - Supply [Max]18 V
Voltage - Supply [Min]3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 1.35
10$ 1.20
Texas InstrumentsTUBE 1$ 1.16
100$ 0.79
250$ 0.61
1000$ 0.40

Description

General part information

CD4098B Series

CD4098B dual monostable multivibrator provides stable retriggerable/resettable one-shot operation for any fixed-voltage timing application.

An external resistor (RX) and an external capacitor (CX) control the timing for the circuit. Adjustment of RXand CXprovides a wide range of output pulse widths from the Q and Q\ terminals. The time delay from trigger input to output transition (trigger progagation delay) and the time delay from set input to output transition (reset progagation delay) are independent of RXand CX.

Leading-edge-triggering (+TR) and trailing-edge-triggering (-TR) input are provided for triggering from either edge of an input pulse. An unused +TR input should be tied to VSS. An unused (-TR) input should be tied to VDD. A RESET (on low level) is provided for immediate termination of the output pulse or to prevent output pulses when power is turned on. An unused RESET input should be tied to VDD. However, if an entire section of the CD4098B is not used, its RESET should be tied to VSS. See Table 1.