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Technical Specifications
Parameters and characteristics for this part
| Specification | SN74AS109N |
|---|---|
| null | |
SN74AS109A Series
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset
| Part | Package / Case | Package / Case | Package / Case | Number of Bits per Element | Trigger Type | Operating Temperature [Max] | Operating Temperature [Min] | Supplier Device Package | Function | Voltage - Supply [Min] | Voltage - Supply [Max] | Max Propagation Delay @ V, Max CL | Clock Frequency | Output Type | Mounting Type | Type | Current - Output High, Low [custom] | Current - Output High, Low [custom] | Number of Elements | Package / Case [x] | Package / Case [y] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
 Texas Instruments | 0.209 " | 16-SOIC | 5.3 mm | 1 | Positive Edge | 70 °C | 0 °C | 16-SO | Reset Set(Preset) | 4.5 V | 5.5 V | 9 ns | 105 MHz | Complementary | Surface Mount | JK Type | 20 mA | 2 mA | 2 | ||
 Texas Instruments | 0.209 " | 16-SOIC | 5.3 mm | 1 | Positive Edge | 70 °C | 0 °C | 16-SO | Reset Set(Preset) | 4.5 V | 5.5 V | 9 ns | 105 MHz | Complementary | Surface Mount | JK Type | 20 mA | 2 mA | 2 | ||
Texas Instruments | |||||||||||||||||||||
 Texas Instruments | 16-SOIC | 1 | Positive Edge | 70 °C | 0 °C | 16-SOIC | Reset Set(Preset) | 4.5 V | 5.5 V | 9 ns | 105 MHz | Complementary | Surface Mount | JK Type | 20 mA | 2 mA | 2 | 0.154 in | 3.9 mm | ||
 Texas Instruments | 0.3 in | 16-DIP | 7.62 mm | 1 | Positive Edge | 70 °C | 0 °C | 16-PDIP | Reset Set(Preset) | 4.5 V | 5.5 V | 9 ns | 105 MHz | Complementary | Through Hole | JK Type | 20 mA | 2 mA | 2 |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Bulk | 761 | $ 0.39 | |
Description
General part information
SN74AS109A Series
These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. Whenandare inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.
The SN54ALS109A and SN54AS109A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS109A and SN74AS109A are characterized for operation from 0°C to 70°C.
These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. Whenandare inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.
Documents
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