74ALVCH16823DGG,11
Obsolete18-BIT BUS-INTERFACE D-TYPE FLIP-FLOP WITH RESET AND ENABLE; 3-STATE
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74ALVCH16823DGG,11
Obsolete18-BIT BUS-INTERFACE D-TYPE FLIP-FLOP WITH RESET AND ENABLE; 3-STATE
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Technical Specifications
Parameters and characteristics for this part
| Specification | 74ALVCH16823DGG,11 |
|---|---|
| Clock Frequency | 350 MHz |
| Current - Output High, Low [custom] | 24 mA |
| Current - Output High, Low [custom] | 24 mA |
| Input Capacitance | 5 pF |
| Max Propagation Delay @ V, Max CL | 3.7 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element [custom] | 9 |
| Number of Elements | 2 |
| Operating Temperature [Max] | 85 C |
| Operating Temperature [Min] | -40 ¯C |
| Output Type | Tri-State |
| Package / Case | 56-TFSOP |
| Package / Case [x] | 0.24 in |
| Package / Case [y] | 6.1 mm |
| Supplier Device Package | 56-TSSOP |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 3.6 V, 2.7 V |
| Voltage - Supply [Min] | 2.3 V, 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | N/A | 0 | $ 1.42 | |
Description
General part information
74ALVCH16823DGG Series
The 74ALVCH16823 is an 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. Incorporates bushold data inputs which eliminate the need for external pull-up resistors to hold unused inputs. The 74ALVCH16823 consists of two sections of nine edge-triggered flip-flops. A clock (nCP) input, an output-enable (nOE) input, a master reset (nMR) input and a clock-enable (nCE) input are provided for each total 9-bit section.
Documents
Technical documentation and resources