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Texas Instruments-TM4C1230C3PMI7R Microcontrollers - MCUs MCU 32-bit ARM Cortex M4F RISC 32KB Flash 1.2V/3.3V 64-Pin LQFP T/R
Integrated Circuits (ICs)

SN74ABTH18504APM

Active
Texas Instruments

SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS

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Texas Instruments-TM4C1230C3PMI7R Microcontrollers - MCUs MCU 32-bit ARM Cortex M4F RISC 32KB Flash 1.2V/3.3V 64-Pin LQFP T/R
Integrated Circuits (ICs)

SN74ABTH18504APM

Active
Texas Instruments

SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74ABTH18504APM
Current - Output High, Low [custom]64 mA
Current - Output High, Low [custom]32 mA
Logic TypeScan Test Universal Bus Transceiver
Mounting TypeSurface Mount
Number of Circuits20-Bit
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Package / Case64-LQFP
Supplier Device Package64-LQFP (10x10)
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
ArrowN/A 160$ 11.07
DigikeyTray 1$ 20.36
10$ 16.26
25$ 15.24
160$ 15.85
320$ 13.45
640$ 13.15
Texas InstrumentsJEDEC TRAY (10+1) 1$ 15.98
100$ 13.96
250$ 10.76
1000$ 9.63

Description

General part information

SN74ABTH18504A Series

The 'ABTH18504A and 'ABTH182504A scan test devices with 20-bit universal bus transceivers are members of the Texas Instruments SCOPETMtestability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, these devices are 20-bit universal bus transceivers that combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPETMuniversal bus transceivers.

Data flow in each direction is controlled by output-enable (and), latch-enable (LEAB and LEBA), clock-enable (and), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched whileis high and/or CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low andis low, A-bus data is stored on a low-to-high transition of CLKAB. Whenis low, the B outputs are active. Whenis high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow, but uses the, LEBA,, and CLKBA inputs.

Documents

Technical documentation and resources

Selecting the Right Level Translation Solution (Rev. A)

Application note

LASP Demo Board User's Guide

EVM User's guide

Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A)

Application note

Programming CPLDs Via the 'LVT8986 LASP

Application note

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Application note

Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A)

Application note

Quad Flatpack No-Lead Logic Packages (Rev. D)

Application note

Advanced Bus Interface Logic Selection Guide

Selection guide

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

Application note

Understanding Advanced Bus-Interface Products Design Guide

Application note

Scan Test Devices With 20-Bit Universal Bus Transceivers datasheet (Rev. C)

Data sheet

Logic Guide (Rev. AB)

Selection guide

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Application note

LOGIC Pocket Data Book (Rev. B)

User guide

An Overview of Bus-Hold Circuit and the Applications (Rev. B)

Application note

Implications of Slow or Floating CMOS Inputs (Rev. E)

Application note

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Application note

TI IBIS File Creation, Validation, and Distribution Processes

Application note

Designing With Logic (Rev. C)

Application note

Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B)

Application note

Input and Output Characteristics of Digital Integrated Circuits

Application note

Live Insertion

Application note