Integrated Circuits (ICs)

CDCVF2505D

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PLL CLOCK DRIVER FOR SYNCH. DRAM & GEN. PURP. APPS W/SPREAD SPECTRUM COMPATIBILITY, POWER DOWN MODE

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Search across all available documentation for this part.

DocumentsDesign and Layout Guidelines for the CDCVF2505 Clock Driver (Rev. A)CDCVF2505 3.3-V Clock Phase-Lock Loop Clock Driver datasheet (Rev. G)

Integrated Circuits (ICs)

CDCVF2505D

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Texas Instruments

PLL CLOCK DRIVER FOR SYNCH. DRAM & GEN. PURP. APPS W/SPREAD SPECTRUM COMPATIBILITY, POWER DOWN MODE

Deep-Dive with AI

DocumentsDesign and Layout Guidelines for the CDCVF2505 Clock Driver (Rev. A)CDCVF2505 3.3-V Clock Phase-Lock Loop Clock Driver datasheet (Rev. G)

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	CDCVF2505D

Differential - Input:Output	False
Divider/Multiplier	False
Frequency - Max [Max]	200 MHz
Mounting Type	Surface Mount
Number of Circuits	1
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output	LVTTL
Package / Case	8-SOIC
Package / Case [x]	0.154 in
Package / Case [y]	3.9 mm
PLL	Yes with Bypass
Ratio - Input:Output	1:5
Supplier Device Package	8-SOIC
Type	PLL Clock Driver
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	3 V

CDCVF2505-Q1 Series

Automotive PLL clock driver for synchronization, DRAM & gen-purpose apps with spread-spectrum compat

Part	Operating Temperature [Max]	Operating Temperature [Min]	Voltage - Supply [Max]	Voltage - Supply [Min]	PLL	Package / Case	Package / Case [custom]	Package / Case [custom]	Type	Number of Circuits	Mounting Type	Supplier Device Package	Ratio - Input:Output	Output	Frequency - Max [Max]	Package / Case [y]	Package / Case [x]	Grade	Qualification
Texas Instruments CDCVF2505PWRG4	85 °C	-40 °C	3.6 V	3 V	Yes with Bypass	8-TSSOP	0.173 "	4.4 mm	PLL Clock Driver	1	Surface Mount	8-TSSOP	1:5	LVTTL	200 MHz
Texas Instruments CDCVF2505PWR	85 °C	-40 °C	3.6 V	3 V	Yes with Bypass	8-TSSOP	0.173 "	4.4 mm	PLL Clock Driver	1	Surface Mount	8-TSSOP	1:5	LVTTL	200 MHz
Texas Instruments CDCVF2505DRG4	85 °C	-40 °C	3.6 V	3 V	Yes with Bypass	8-SOIC			PLL Clock Driver	1	Surface Mount	8-SOIC	1:5	LVTTL	200 MHz	3.9 mm	0.154 in
Texas Instruments CDCVF2505D	85 °C	-40 °C	3.6 V	3 V	Yes with Bypass	8-SOIC			PLL Clock Driver	1	Surface Mount	8-SOIC	1:5	LVTTL	200 MHz	3.9 mm	0.154 in
Texas Instruments CDCVF2505PW	85 °C	-40 °C	3.6 V	3 V	Yes with Bypass	8-TSSOP	0.173 "	4.4 mm	PLL Clock Driver	1	Surface Mount	8-TSSOP	1:5	LVTTL	200 MHz
Texas Instruments CDCVF2505DG4	85 °C	-40 °C	3.6 V	3 V	Yes with Bypass	8-SOIC			PLL Clock Driver	1	Surface Mount	8-SOIC	1:5	LVTTL	200 MHz	3.9 mm	0.154 in
Texas Instruments CDCVF2505IDRQ1	85 °C	-40 °C	3.6 V	3 V	Yes with Bypass	8-SOIC			PLL Clock Driver	1	Surface Mount	8-SOIC	1:5	LVTTL	200 MHz	3.9 mm	0.154 in	Automotive	AEC-Q100
Texas Instruments CDCVF2505DR	85 °C	-40 °C	3.6 V	3 V	Yes with Bypass	8-SOIC			PLL Clock Driver	1	Surface Mount	8-SOIC	1:5	LVTTL	200 MHz	3.9 mm	0.154 in

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tube	1	$ 3.54
		10	$ 3.18
		75	$ 3.01
		150	$ 2.61
		300	$ 2.47
		525	$ 2.22
		1050	$ 1.87
		2550	$ 1.78
		5025	$ 1.71
Texas Instruments	TUBE	1	$ 2.75
		100	$ 2.41
		250	$ 1.69
		1000	$ 1.36

Description

General part information

CDCVF2505-Q1 Series

The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks (1Y[0–3] and CLKOUT) to the input clock signal (CLKIN). The CDCVF2505 operates at 3.3 V. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50 percent, independent of duty cycle at CLKIN. The device automatically goes in power-down mode when no input signal is applied to CLKIN.

Unlike many products containing PLLs, the CDCVF2505 does not require an external RC network. The loop filter for the PLLs is included on-chip, minimizing component count, space, and cost.

Documents

Technical documentation and resources

Design and Layout Guidelines for the CDCVF2505 Clock Driver (Rev. A)

Application note

CDCVF2505 3.3-V Clock Phase-Lock Loop Clock Driver datasheet (Rev. G)

Data sheet