The MEC1725 is a family of low power integrated embedded controller designed for notebook applications storage enclosure platforms. The MEC1725 is a highly-configurable, mixed-signal, advanced I/O controller. It contains a 32-bit ARM® Cortex-M4F processor core with closely-coupled memory for optimal code execution and data access. An internal ROM, embedded in the design, is used to store the power on/boot sequence and APIs available during run time.

When VTR\_CORE is applied to the device, the secure bootloader API is used to download the custom firmware image from the system’s shared SPI Flash device, thereby allowing system designers to customize the device’s behavior. The MEC1725 device is directly powered by a minimum of two separate suspend supply planes (VBAT and VTR) and senses a third runtime power plane (VCC) to provide "instant on" and system power management functions. The MEC1725 has two banks of I/O pins that are able to operate at either 3.3 V or 1.8 V. Operating at 1.8V allows the MEC1725 to interface with the latest platform controller hubs and will lower the overall power consumed by the device, Whereas 3.3V allows this device to be integrated into legacy platforms that require 3.3V operation.

The MEC1725 host interface is the Intel® Enhanced Serial Peripheral Interface (eSPI). The eSPI Interface is a 1.8V interface that operates in single, double and quad I/O modes. The eSPI Interface supports all four eSPI channels: Peripheral Channel, Virtual Wires Channel, OOB Message Channel, and Run-time Flash Access Channel. The eSPI hardware Flash Access Channel is used by the Boot ROM to support Master Attached Flash Sharing (MAFS). In addition, the MEC1725 has specially designed hardware to support Slave Attached Flash Sharing (SAFS). The eSPI SAFS Bridge imposes Region-Based Protection and Locking security feature, which limits access to certain regions of the flash to specific masters. There may be one or more masters (e.g., BIOS, ME, etc) that will access the SAF via the eSPI interface. The ARM® Cortex-M4F processor is also considered a master, which will also have its access limited to EC only regions of SPI Flash as determined by the customer firmware application.The MEC1725 secure bootloader authenticates and optionally decrypts the SPI Flash OEM boot image using the AES-256, ECDSA, SHA-512 cryptographic hardware accelerators. The MEC1725 hardware accelerators support 128-bit and 256-bit AES encryption, ECDSA and EC\_KCDSA signing algorithms, 1024-bits to 4096-bits RSA and Elliptic asymmetric public key algorithms, and a True Random Number Generator (TRNG). Runtime APIs are provided in the ROM for customer application code to use the cryptographic hardware. Additionally, the device offers lockable OTP storage for private keys and IDs.Read more