Deep-Dive with AI
Search across all available documentation for this part.
Technical Specifications
Parameters and characteristics for this part
| Specification | DM385AAARD21F |
|---|---|
| Interface | SPI, SD, IrDA, I2C, Ethernet, McASP, PCI, UART/USART, USB |
| Mounting Type | Surface Mount |
| Non-Volatile Memory | 48 kB |
| On-Chip RAM | 640 kB |
| Operating Temperature [Max] | 95 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 609-LFBGA, FCBGA |
| Supplier Device Package | 609-FCBGA (16x16) |
| Type | Digital Media System-on-Chip (DMSoC) |
| Voltage - Core | 1.1 V, 1.2 V, 1.35 V |
| Voltage - I/O | 1.5 V, 1.35 V, 3.3 V, 1.8 V |
DM385 Series
DaVinci Digital Media Processor
| Part | Voltage - I/O | Non-Volatile Memory | Type | Package / Case | Clock Rate | Supplier Device Package | Operating Temperature [Max] | Operating Temperature [Min] | Mounting Type | On-Chip RAM | Interface | Voltage - Core |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments | 1.35 V 1.5 V 1.8 V 3.3 V | 48 kB | Digital Media System-on-Chip (DMSoC) | 609-LFBGA FCBGA | 720 MHz | 609-FCBGA (16x16) | 95 °C | 0 °C | Surface Mount | 640 kB | Ethernet I2C IrDA McASP PCI SD SPI UART/USART USB | 1.1 V 1.2 V 1.35 V |
 Texas Instruments | 1.35 V 1.5 V 1.8 V 3.3 V | 48 kB | Digital Media System-on-Chip (DMSoC) | 609-LFBGA FCBGA | 970 MHz | 609-FCBGA (16x16) | 95 °C | 0 °C | Surface Mount | 640 kB | Ethernet I2C IrDA McASP PCI SD SPI UART/USART USB | 1.1 V 1.2 V 1.35 V |
Texas Instruments | 1.35 V 1.5 V 1.8 V 3.3 V | 48 kB | Digital Media System-on-Chip (DMSoC) | 609-LFBGA FCBGA | 609-FCBGA (16x16) | 95 °C | -40 °C | Surface Mount | 640 kB | Ethernet I2C IrDA McASP PCI SD SPI UART/USART USB | 1.1 V 1.2 V 1.35 V | |
 Texas Instruments | 1.35 V 1.5 V 1.8 V 3.3 V | 48 kB | Digital Media System-on-Chip (DMSoC) | 609-LFBGA FCBGA | 970 MHz | 609-FCBGA (16x16) | 95 °C | 0 °C | Surface Mount | 640 kB | Ethernet I2C IrDA McASP PCI SD SPI UART/USART USB | 1.1 V 1.2 V 1.35 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 90 | $ 40.46 | |
| Texas Instruments | JEDEC TRAY (5+1) | 1 | $ 49.53 | |
| 100 | $ 44.02 | |||
| 250 | $ 36.19 | |||
| 1000 | $ 32.37 | |||
Description
General part information
DM385 Series
DM385 and DM388 DaVinci Digital Media Processors are a highly integrated, cost-effective, low-power, programmable platform that leverages TI’s DaVinci processor technology to meet the processing needs of HD Video Conferencing - Skype endpoints, IP Netcam, Digital Signage, Media Players and Adapters, Mobile Medical Imaging, Network Projectors, Home Audio and Video Equipment, and similar devices in SD, HD, and 4K x 2K resolutions. The Programmable High-Definition Video Image Processor of the device supports 1080p60 of real time H.264BP/MP/HP video encode or decode. The included best-in-class H.264 encoder provides high-quality video encode for the lowest possible bit rate under all conditions, reducing valuable storage space to a minimum. In addition, the device also supports other video codecs such as MJPEG, MPEG-2, and MPEG-4. The device provides a full set of video preprocessing and postprocessing functions to ensure the best video quality. The low power consumption and high performance of the device makes it particularly suitable for portable and automotive applications. The DM388 is uniquely capable of running the Fourth-Generation Motion-Compensated Noise Filtering technology of TI.
The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device also combines programmable video and audio processing with a highly integrated peripheral set.
The device processors include a high-definition video and imaging coprocessor 2 (HDVICP2), to off-load many video and imaging processing tasks for common video and imaging algorithms. Programmability is provided by an ARM Cortex-A8 RISC CPU with NEON extension and high-definition video and imaging coprocessors. The ARM lets developers separate control functions from A/V algorithms programmed on coprocessors, thus reducing the complexity of the system software. The ARM Cortex-A8 32-bit RISC processor with NEON floating-point extension includes: 32KB of instruction cache; 32KB of data cache; 256KB of L2 cache with ECC; 48KB of boot ROM; and 64KB of RAM.