Catalog
DaVinci Digital Media Processor
Key Features
• High-Performance DaVinci Digital Media ProcessorsUp to 1000-MHz ARM® Cortex™-A8 RISC ProcessorUp to 2000 ARM Cortex-A8 MIPSARM Cortex-A8 CoreARMv7 ArchitectureIn-Order, Dual-Issue, Superscalar Processor CoreNEON™ Multimedia ArchitectureSupports Integer and Floating PointJazelle® RCT Execution EnvironmentARM Cortex-A8 Memory Architecture32KB of Instruction and Data Caches256KB of L2 Cache with ECC64KB of RAM, 48KB of Boot ROM256KB of On-Chip Memory Controller (OCMC) RAMImaging Subsystem (ISS)Camera Sensor ConnectionParallel Connection for Raw (up to 16-Bit) and BT.656/BT.1120 (8- or 16-Bit)CSI2 Serial ConnectionImage Sensor Interface (ISIF) for Handling Image and Video Data From the Camera SensorImage Pipe Interface (IPIPEIF) for Image and Video Data Connection Between Camera Sensor, ISIF, IPIPE, and DRAMImage Pipe (IPIPE) for Real-Time Image and Video ProcessingResizerResizing Image and Video From 1/16x to 8xGenerating Two Different Resizing Outputs ConcurrentlyHardware 3A Engine (H3A) for Generating Key Statistics for 3A (AE, AWB, and AF) ControlFace Detect (FD) EngineHardware Face Detection for up to 35 Faces Per FrameProgrammable High-Definition Video Image Coprocessing (HDVICP v2) EngineEncode, Decode, Transcode OperationsH.264 BP/MP/HP, MPEG-2, VC-1, MPEG-4 SP/ASP, JPEG/MJPEGFourth-Generation Motion-Compensated Noise Filter (DM388 Only)Media ControllerControls the HDVPSS, HDVICP2, and ISSEndiannessARM Instructions and Data – Little EndianHD Video Processing Subsystem (HDVPSS)Two 165-MHz HD Video Capture InputsOne 16- or 24-Bit Input, Splittable Into Dual 8-Bit SD Capture PortsOne 8-, 16-, or 24-Bit HD Input and 8-Bit SD Input Capture PortTwo 165-MHz HD Video Display OutputsOne 16-, 24-, or 30-Bit and One 16- or 24-Bit OutputComponent HD Analog OutputComposite Analog OutputDigital HDMI 1.3 Transmitter with Integrated PHYAdvanced Video Processing Features Such as Scan, Format, and Rate ConversionThree Graphics Layers and Compositors32-Bit DDR2, DDR3, and DDR3L SDRAM InterfaceSupports up to 400 MHz for DDR2, 533 MHz for DDR3, and 533 MHz for DDR3LUp to Two x 16 Devices, 2GB of Total Address SpaceDynamic Memory Manager (DMM)Programmable Multi-Zone Memory MappingEnables Efficient 2D Block AccessesSupports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and MirroringGeneral-Purpose Memory Controller (GPMC)8- or 16-Bit Multiplexed Address and Data Bus512MB of Total Address Space Divided Among up to 8 Chip SelectsGlueless Interface to NOR Flash, NAND Flash (BCH/Hamming Error Code Detection), SRAM and Pseudo-SRAMError Locator Module (ELM) Outside of GPMC to Provide up to 16-Bit or 512-Byte Hardware ECC for NANDFlexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs, and MoreEnhanced Direct Memory Access (EDMA) ControllerFour Transfer Controllers64 Independent DMA Channels8 QDMA ChannelsEthernet Switch with Dual 10-, 100-, or1000-Mbps External Interfaces (EMAC Software)IEEE 802.3 Compliant (3.3-V I/O Only)MII/RMII/GMII/RGMII Media Independent InterfacesManagement Data I/O (MDIO) ModuleReset IsolationIEEE 1588 Time-Stamping and Industrial Ethernet ProtocolsDual USB 2.0 Ports with Integrated PHYsUSB2.0 High- and Full-Speed ClientsUSB2.0 High-, Full-, and Low-Speed HostsSupports End Points 0-15One PCI Express 2.0 Port with Integrated PHYSupported onAll DM385 DevicesDM388 Devices with PCIe EnabledSingle Port with 1 Lane at 5.0 GT/sConfigurable as Root Complex or EndpointEight 32-Bit General-Purpose Timers (Timer1–8)One System Watchdog Timer (WDT0)Three Configurable UART/IrDA/CIR ModulesUART0 with Modem Control SignalsSupports up to 3.6864 MbpsSIR, MIR, FIR (4.0 MBAUD), and CIRFour Serial Peripheral Interfaces (SPIs) (up to 48 MHz)Each with Four Chip SelectsThree MMC/SD/SDIO Serial Interfaces (up to 48 MHz)Supporting up to 1-, 4-, or 8-Bit ModesFour Inter-Integrated Circuit (I2C Bus™) PortsTwo Multichannel Audio Serial Ports (McASP)Six Serializer Transmit and Receive PortsTwo Serializer Transmit and Receive PortsDIT-Capable For S/PDIF (All Ports)Four Audio Tracking Logic (ATL) ModulesReal-Time Clock (RTC)One-Time or Periodic Interrupt GenerationUp to 125 General-Purpose I/O (GPIO) PinsOne Spin Lock Module with up to 128 Hardware SemaphoresOne Mailbox Module with 12 MailboxesOn-Chip ARM ROM Bootloader (RBL)Power, Reset, and Clock ManagementSmartReflex™ Technology (Level 2b)Multiple Independent Core Power DomainsMultiple Independent Core Voltage DomainsSupport for Multiple Operating Points per Voltage DomainClock Enable and Disable Control for Subsystems and Peripherals32KB of Embedded Trace Buffer™ (ETB™) and 5-pin Trace Interface for DebugIEEE 1149.1 (JTAG) Compatible609-Pin Pb-Free BGA Package (AAR Suffix), 0.8-mm Effective Pitch with Via Channel Technology to Reduce PCB Cost (0.5-mm Ball Spacing)45-nm CMOS Technology1.8- and 3.3-V Dual Voltage Buffers for General I/OAll trademarks are the property of their respective owners.High-Performance DaVinci Digital Media ProcessorsUp to 1000-MHz ARM® Cortex™-A8 RISC ProcessorUp to 2000 ARM Cortex-A8 MIPSARM Cortex-A8 CoreARMv7 ArchitectureIn-Order, Dual-Issue, Superscalar Processor CoreNEON™ Multimedia ArchitectureSupports Integer and Floating PointJazelle® RCT Execution EnvironmentARM Cortex-A8 Memory Architecture32KB of Instruction and Data Caches256KB of L2 Cache with ECC64KB of RAM, 48KB of Boot ROM256KB of On-Chip Memory Controller (OCMC) RAMImaging Subsystem (ISS)Camera Sensor ConnectionParallel Connection for Raw (up to 16-Bit) and BT.656/BT.1120 (8- or 16-Bit)CSI2 Serial ConnectionImage Sensor Interface (ISIF) for Handling Image and Video Data From the Camera SensorImage Pipe Interface (IPIPEIF) for Image and Video Data Connection Between Camera Sensor, ISIF, IPIPE, and DRAMImage Pipe (IPIPE) for Real-Time Image and Video ProcessingResizerResizing Image and Video From 1/16x to 8xGenerating Two Different Resizing Outputs ConcurrentlyHardware 3A Engine (H3A) for Generating Key Statistics for 3A (AE, AWB, and AF) ControlFace Detect (FD) EngineHardware Face Detection for up to 35 Faces Per FrameProgrammable High-Definition Video Image Coprocessing (HDVICP v2) EngineEncode, Decode, Transcode OperationsH.264 BP/MP/HP, MPEG-2, VC-1, MPEG-4 SP/ASP, JPEG/MJPEGFourth-Generation Motion-Compensated Noise Filter (DM388 Only)Media ControllerControls the HDVPSS, HDVICP2, and ISSEndiannessARM Instructions and Data – Little EndianHD Video Processing Subsystem (HDVPSS)Two 165-MHz HD Video Capture InputsOne 16- or 24-Bit Input, Splittable Into Dual 8-Bit SD Capture PortsOne 8-, 16-, or 24-Bit HD Input and 8-Bit SD Input Capture PortTwo 165-MHz HD Video Display OutputsOne 16-, 24-, or 30-Bit and One 16- or 24-Bit OutputComponent HD Analog OutputComposite Analog OutputDigital HDMI 1.3 Transmitter with Integrated PHYAdvanced Video Processing Features Such as Scan, Format, and Rate ConversionThree Graphics Layers and Compositors32-Bit DDR2, DDR3, and DDR3L SDRAM InterfaceSupports up to 400 MHz for DDR2, 533 MHz for DDR3, and 533 MHz for DDR3LUp to Two x 16 Devices, 2GB of Total Address SpaceDynamic Memory Manager (DMM)Programmable Multi-Zone Memory MappingEnables Efficient 2D Block AccessesSupports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and MirroringGeneral-Purpose Memory Controller (GPMC)8- or 16-Bit Multiplexed Address and Data Bus512MB of Total Address Space Divided Among up to 8 Chip SelectsGlueless Interface to NOR Flash, NAND Flash (BCH/Hamming Error Code Detection), SRAM and Pseudo-SRAMError Locator Module (ELM) Outside of GPMC to Provide up to 16-Bit or 512-Byte Hardware ECC for NANDFlexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs, and MoreEnhanced Direct Memory Access (EDMA) ControllerFour Transfer Controllers64 Independent DMA Channels8 QDMA ChannelsEthernet Switch with Dual 10-, 100-, or1000-Mbps External Interfaces (EMAC Software)IEEE 802.3 Compliant (3.3-V I/O Only)MII/RMII/GMII/RGMII Media Independent InterfacesManagement Data I/O (MDIO) ModuleReset IsolationIEEE 1588 Time-Stamping and Industrial Ethernet ProtocolsDual USB 2.0 Ports with Integrated PHYsUSB2.0 High- and Full-Speed ClientsUSB2.0 High-, Full-, and Low-Speed HostsSupports End Points 0-15One PCI Express 2.0 Port with Integrated PHYSupported onAll DM385 DevicesDM388 Devices with PCIe EnabledSingle Port with 1 Lane at 5.0 GT/sConfigurable as Root Complex or EndpointEight 32-Bit General-Purpose Timers (Timer1–8)One System Watchdog Timer (WDT0)Three Configurable UART/IrDA/CIR ModulesUART0 with Modem Control SignalsSupports up to 3.6864 MbpsSIR, MIR, FIR (4.0 MBAUD), and CIRFour Serial Peripheral Interfaces (SPIs) (up to 48 MHz)Each with Four Chip SelectsThree MMC/SD/SDIO Serial Interfaces (up to 48 MHz)Supporting up to 1-, 4-, or 8-Bit ModesFour Inter-Integrated Circuit (I2C Bus™) PortsTwo Multichannel Audio Serial Ports (McASP)Six Serializer Transmit and Receive PortsTwo Serializer Transmit and Receive PortsDIT-Capable For S/PDIF (All Ports)Four Audio Tracking Logic (ATL) ModulesReal-Time Clock (RTC)One-Time or Periodic Interrupt GenerationUp to 125 General-Purpose I/O (GPIO) PinsOne Spin Lock Module with up to 128 Hardware SemaphoresOne Mailbox Module with 12 MailboxesOn-Chip ARM ROM Bootloader (RBL)Power, Reset, and Clock ManagementSmartReflex™ Technology (Level 2b)Multiple Independent Core Power DomainsMultiple Independent Core Voltage DomainsSupport for Multiple Operating Points per Voltage DomainClock Enable and Disable Control for Subsystems and Peripherals32KB of Embedded Trace Buffer™ (ETB™) and 5-pin Trace Interface for DebugIEEE 1149.1 (JTAG) Compatible609-Pin Pb-Free BGA Package (AAR Suffix), 0.8-mm Effective Pitch with Via Channel Technology to Reduce PCB Cost (0.5-mm Ball Spacing)45-nm CMOS Technology1.8- and 3.3-V Dual Voltage Buffers for General I/OAll trademarks are the property of their respective owners.
Description
AI
DM385 and DM388 DaVinci Digital Media Processors are a highly integrated, cost-effective, low-power, programmable platform that leverages TI’s DaVinci processor technology to meet the processing needs of HD Video Conferencing - Skype endpoints, IP Netcam, Digital Signage, Media Players and Adapters, Mobile Medical Imaging, Network Projectors, Home Audio and Video Equipment, and similar devices in SD, HD, and 4K x 2K resolutions. The Programmable High-Definition Video Image Processor of the device supports 1080p60 of real time H.264BP/MP/HP video encode or decode. The included best-in-class H.264 encoder provides high-quality video encode for the lowest possible bit rate under all conditions, reducing valuable storage space to a minimum. In addition, the device also supports other video codecs such as MJPEG, MPEG-2, and MPEG-4. The device provides a full set of video preprocessing and postprocessing functions to ensure the best video quality. The low power consumption and high performance of the device makes it particularly suitable for portable and automotive applications. The DM388 is uniquely capable of running the Fourth-Generation Motion-Compensated Noise Filtering technology of TI.
The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device also combines programmable video and audio processing with a highly integrated peripheral set.
The device processors include a high-definition video and imaging coprocessor 2 (HDVICP2), to off-load many video and imaging processing tasks for common video and imaging algorithms. Programmability is provided by an ARM Cortex-A8 RISC CPU with NEON extension and high-definition video and imaging coprocessors. The ARM lets developers separate control functions from A/V algorithms programmed on coprocessors, thus reducing the complexity of the system software. The ARM Cortex-A8 32-bit RISC processor with NEON floating-point extension includes: 32KB of instruction cache; 32KB of data cache; 256KB of L2 cache with ECC; 48KB of boot ROM; and 64KB of RAM.
The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections in this document and the associated peripheral reference guides. The peripheral set includes: HD Video Processing Subsystem; Dual-Port Gigabit Ethernet MACs (10/100/1000 Mbps) (Ethernet Switch) with MII/RMII/GMII/RGMII and MDIO interface supporting IEEE 1588 Time-Stamping, and Industrial Ethernet Protocols; two USB ports with integrated 2.0 PHY; PCIe x1 GEN2-Compliant interface; two serializer McASP audio serial ports (with DIT mode); three UARTs with IrDA and CIR support; four SPI serial interfaces; a CSI2 serial connection; three MMC/SD/SDIO serial interfaces; four I2C master and slave interfaces; a parallel camera interface (CAM); up to 125 general-purpose I/Os (GPIOs); eight 32-bit general-purpose timers; system watchdog timer; DDR2/DDR3/DDR3L SDRAM interface; flexible 8- or 16-bit asynchronous memory interface; a Spin Lock; and Mailbox.
Additionally, TI provides a complete set of development tools for the ARM which include C compilers and a Microsoft® Windows® debugger interface for visibility into source code execution.
DM385 and DM388 DaVinci Digital Media Processors are a highly integrated, cost-effective, low-power, programmable platform that leverages TI’s DaVinci processor technology to meet the processing needs of HD Video Conferencing - Skype endpoints, IP Netcam, Digital Signage, Media Players and Adapters, Mobile Medical Imaging, Network Projectors, Home Audio and Video Equipment, and similar devices in SD, HD, and 4K x 2K resolutions. The Programmable High-Definition Video Image Processor of the device supports 1080p60 of real time H.264BP/MP/HP video encode or decode. The included best-in-class H.264 encoder provides high-quality video encode for the lowest possible bit rate under all conditions, reducing valuable storage space to a minimum. In addition, the device also supports other video codecs such as MJPEG, MPEG-2, and MPEG-4. The device provides a full set of video preprocessing and postprocessing functions to ensure the best video quality. The low power consumption and high performance of the device makes it particularly suitable for portable and automotive applications. The DM388 is uniquely capable of running the Fourth-Generation Motion-Compensated Noise Filtering technology of TI.
The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device also combines programmable video and audio processing with a highly integrated peripheral set.
The device processors include a high-definition video and imaging coprocessor 2 (HDVICP2), to off-load many video and imaging processing tasks for common video and imaging algorithms. Programmability is provided by an ARM Cortex-A8 RISC CPU with NEON extension and high-definition video and imaging coprocessors. The ARM lets developers separate control functions from A/V algorithms programmed on coprocessors, thus reducing the complexity of the system software. The ARM Cortex-A8 32-bit RISC processor with NEON floating-point extension includes: 32KB of instruction cache; 32KB of data cache; 256KB of L2 cache with ECC; 48KB of boot ROM; and 64KB of RAM.
The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections in this document and the associated peripheral reference guides. The peripheral set includes: HD Video Processing Subsystem; Dual-Port Gigabit Ethernet MACs (10/100/1000 Mbps) (Ethernet Switch) with MII/RMII/GMII/RGMII and MDIO interface supporting IEEE 1588 Time-Stamping, and Industrial Ethernet Protocols; two USB ports with integrated 2.0 PHY; PCIe x1 GEN2-Compliant interface; two serializer McASP audio serial ports (with DIT mode); three UARTs with IrDA and CIR support; four SPI serial interfaces; a CSI2 serial connection; three MMC/SD/SDIO serial interfaces; four I2C master and slave interfaces; a parallel camera interface (CAM); up to 125 general-purpose I/Os (GPIOs); eight 32-bit general-purpose timers; system watchdog timer; DDR2/DDR3/DDR3L SDRAM interface; flexible 8- or 16-bit asynchronous memory interface; a Spin Lock; and Mailbox.
Additionally, TI provides a complete set of development tools for the ARM which include C compilers and a Microsoft® Windows® debugger interface for visibility into source code execution.
