Deep-Dive with AI
Search across all available documentation for this part.
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | ADS58J89IRGCT |
|---|---|
| Data Interface | JESD204B |
| Mounting Type | Surface Mount |
| Number of Channels | 4 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 64-VFQFN Exposed Pad |
| Resolution (Bits) | 14 b |
| Sampling Rate (Per Second) | 500 M |
| Supplier Device Package | 64-VQFN (9x9) |
| Type | Receiver |
| Voltage - Supply [Max] | 2 V, 3.45 V |
| Voltage - Supply [Min] | 1.7 V, 3.15 V |
| Voltage Supply Source | Analog and Digital |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 393.44 | |
| Digi-Reel® | 1 | $ 393.44 | ||
| Tape & Reel (TR) | 250 | $ 366.12 | ||
| Texas Instruments | SMALL T&R | 1 | $ 339.76 | |
| 100 | $ 307.54 | |||
| 250 | $ 298.75 | |||
| 1000 | $ 292.89 | |||
Description
General part information
ADS58J89 Series
The ADS58J89 is a high-linearity, quad-channel, 14-bit, 250/500-MSPS IF (intermediate frequency) receiver. The four channels contain 500MSPS 14-bit ADCs followed by signal processing for wireless infrastructure systems. The channels can be configured in various modes depending on bandwidth, resolution and sample time requirements. The signal processing block contains selectable modes for decimation filters, SNR Boost filters, resolution versus time and time-division duplex (TDD) burst mode. Designed for high antenna count systems, the 4 channels provides high bandwidth and linearity to multi-channel receivers in a small footprint. The device can be dual function as traffic receiver and power amplifier linearization feedback path in TDD systems.
Key Specifications:
The ADS58J89 is a high-linearity, quad-channel, 14-bit, 250/500-MSPS IF (intermediate frequency) receiver. The four channels contain 500MSPS 14-bit ADCs followed by signal processing for wireless infrastructure systems. The channels can be configured in various modes depending on bandwidth, resolution and sample time requirements. The signal processing block contains selectable modes for decimation filters, SNR Boost filters, resolution versus time and time-division duplex (TDD) burst mode. Designed for high antenna count systems, the 4 channels provides high bandwidth and linearity to multi-channel receivers in a small footprint. The device can be dual function as traffic receiver and power amplifier linearization feedback path in TDD systems.
Documents
Technical documentation and resources
