ADS58J89 Series

Quad 500MSPS Receiver and Feedback IC

Catalog

Quad 500MSPS Receiver and Feedback IC

Part	Data Interface	Type	Package / Case	Operating Temperature [Max]	Operating Temperature [Min]	Sampling Rate (Per Second)	Resolution (Bits)	Supplier Device Package	Voltage - Supply	Mounting Type	Voltage Supply Source	Number of Channels	Voltage - Supply [Max]	Voltage - Supply [Min]
Texas Instruments ADS58J89IRGCR	JESD204B	Receiver	64-VFQFN Exposed Pad	125 °C	-40 °C	500 M	14 b	64-VQFN (9x9)	1.8 V 3.3 V	Surface Mount	Analog and Digital	4
Texas Instruments ADS58J89IRGCT	JESD204B	Receiver	64-VFQFN Exposed Pad	85 °C	-40 °C	500 M	14 b	64-VQFN (9x9)		Surface Mount	Analog and Digital	4	2 V 3.45 V	1.7 V 3.15 V

Catalog

Quad 500MSPS Receiver and Feedback IC

Key Features

• 4-Ch, 14-Bit 500MSPS With Digital Signal ProcessingPower Amplifier Linearization (Feedback) Modes14-Bits Every Other Sample at 250MSPSProgrammable Resolution vs Duty CycleDuty Cycle 3:2 (60% 11-Bit, 40% 9-Bit)Duty Cycle 2:3 (40% 12-Bit, 60% 9-Bit)Duty Cycle 1:3 (25% 14-Bit, 75% 9-Bit)Traffic Receiver Modes14-Bit 250MSPS: Decimate by 2 Filter, High/Low Pass9-Bit SNR-Boost Filter (150-MHz Max Bandwidth)9-to-14-Bit TDD Burst (200-MHz Max Bandwidth)Flexible Input Clock Buffer With Divide by 1/2/4JESD204B Digital Interface up to 5.0Gbps1 or 2 Lanes per Channel, With Subclass 164-Pin VQFN Package (9 × 9 mm)4-Ch, 14-Bit 500MSPS With Digital Signal ProcessingPower Amplifier Linearization (Feedback) Modes14-Bits Every Other Sample at 250MSPSProgrammable Resolution vs Duty CycleDuty Cycle 3:2 (60% 11-Bit, 40% 9-Bit)Duty Cycle 2:3 (40% 12-Bit, 60% 9-Bit)Duty Cycle 1:3 (25% 14-Bit, 75% 9-Bit)Traffic Receiver Modes14-Bit 250MSPS: Decimate by 2 Filter, High/Low Pass9-Bit SNR-Boost Filter (150-MHz Max Bandwidth)9-to-14-Bit TDD Burst (200-MHz Max Bandwidth)Flexible Input Clock Buffer With Divide by 1/2/4JESD204B Digital Interface up to 5.0Gbps1 or 2 Lanes per Channel, With Subclass 164-Pin VQFN Package (9 × 9 mm)

Description

The ADS58J89 is a high-linearity, quad-channel, 14-bit, 250/500-MSPS IF (intermediate frequency) receiver. The four channels contain 500MSPS 14-bit ADCs followed by signal processing for wireless infrastructure systems. The channels can be configured in various modes depending on bandwidth, resolution and sample time requirements. The signal processing block contains selectable modes for decimation filters, SNR Boost filters, resolution versus time and time-division duplex (TDD) burst mode. Designed for high antenna count systems, the 4 channels provides high bandwidth and linearity to multi-channel receivers in a small footprint. The device can be dual function as traffic receiver and power amplifier linearization feedback path in TDD systems. Key Specifications: The ADS58J89 is a high-linearity, quad-channel, 14-bit, 250/500-MSPS IF (intermediate frequency) receiver. The four channels contain 500MSPS 14-bit ADCs followed by signal processing for wireless infrastructure systems. The channels can be configured in various modes depending on bandwidth, resolution and sample time requirements. The signal processing block contains selectable modes for decimation filters, SNR Boost filters, resolution versus time and time-division duplex (TDD) burst mode. Designed for high antenna count systems, the 4 channels provides high bandwidth and linearity to multi-channel receivers in a small footprint. The device can be dual function as traffic receiver and power amplifier linearization feedback path in TDD systems. Key Specifications: