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56-TSSOP
Integrated Circuits (ICs)

SN74ALVCH16270DLR

Active
Texas Instruments

12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

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DocumentsDatasheetLive Insertion+17
56-TSSOP
Integrated Circuits (ICs)

SN74ALVCH16270DLR

Active
Texas Instruments

12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

Deep-Dive with AI

DocumentsDatasheetLive Insertion+17

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74ALVCH16270DLR
Current - Output High, Low24 mA
Logic TypeRegistered Bus Exchanger
Mounting TypeSurface Mount
Number of Circuits [Max]24 Bit
Number of Circuits [Min]12
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Package / Case0.295 in
Package / Case56-BSSOP
Package / Case7.5 mm
Supplier Device Package56-SSOP
Voltage - Supply [Max]3.6 V
Voltage - Supply [Min]1.65 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 2.38
Digi-Reel® 1$ 2.38
Tape & Reel (TR) 1000$ 1.17
2000$ 1.09
5000$ 1.05
Texas InstrumentsLARGE T&R 1$ 1.79
100$ 1.48
250$ 1.06
1000$ 0.80

Description

General part information

SN74ALVCH16270 Series

This 12-bit to 24-bit registered bus exchanger is designed for 1.65-V to 3.6-V VCCoperation.

The SN74ALVCH16270 is used in applications in which data must be transferred from a narrow high-speed bus to a wide lower-frequency bus.

The device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input when the appropriate CLKEN\ inputs are low. The select (SEL)\ line selects 1B or 2B data for the A outputs. For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of the CLKENA\ inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables (OEA\, OEB\). The control terminals are registered to synchronize the bus-direction changes with CLK.