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Analog Devices-DS1245Y-70IND+ NVRAM NVRAM NVSRAM Parallel 1Mbit 5V 32-Pin EDIP Tube
Integrated Circuits (ICs)

DS1245Y-70+

Active
Analog Devices Inc./Maxim Integrated

NVRAM NVSRAM PARALLEL 1MBIT 5V 32-PIN EDIP TUBE

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Analog Devices-DS1245Y-70IND+ NVRAM NVRAM NVSRAM Parallel 1Mbit 5V 32-Pin EDIP Tube
Integrated Circuits (ICs)

DS1245Y-70+

Active
Analog Devices Inc./Maxim Integrated

NVRAM NVSRAM PARALLEL 1MBIT 5V 32-PIN EDIP TUBE

Technical Specifications

Parameters and characteristics for this part

SpecificationDS1245Y-70+
Access Time70 ns
Memory FormatNVSRAM
Memory InterfaceParallel
Memory Organization128 K
Memory Size1 Mbit
Memory TypeNon-Volatile
Mounting TypeThrough Hole
Operating Temperature [Max]70 °C
Operating Temperature [Min]0 °C
Package / Case32-DIP Module
Package / Case15.24 mm
Package / Case0.6 in
Supplier Device Package32-EDIP
TechnologyNVSRAM (Non-Volatile SRAM)
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V
Write Cycle Time - Word, Page70 ns

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$Updated
DigikeyTube 1$ 61.42<4d
11$ 56.51
33$ 54.30
55$ 53.29
110$ 51.94

Description

General part information

DS1245Y Series

The DS1245 1024k Nonvolatile (NV) SRAMs are 1,048,576-bit, fully static, nonvolatile SRAMs organized as 131,072 words by 8 bits. Each complete NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors VCCfor an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is nconditionally enabled to prevent data corruption. DIP-package DS1245 devices can be used in place of existing 128k x 8 static RAMs directly conforming to the popular bytewide 32-pin DIP standard. DS1245 devices in the PowerCap Module package are directly surface mountable and are normally paired with a DS9034PC PowerCap to form a complete Nonvolatile SRAM module. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.