Zenode.ai Logo
Beta
20-pin (PW) package image
Integrated Circuits (ICs)

SN74HC373PW

Obsolete
Texas Instruments

OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

Deep-Dive with AI

Search across all available documentation for this part.

20-pin (PW) package image
Integrated Circuits (ICs)

SN74HC373PW

Obsolete
Texas Instruments

OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74HC373PW
Circuit [custom]8
Circuit [custom]8
Current - Output High, Low [custom]7.8 mA
Current - Output High, Low [custom]7.8 mA
Delay Time - Propagation15 ns
Independent Circuits1
Logic TypeD-Type Transparent Latch
Mounting TypeSurface Mount
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output TypeTri-State
Package / Case20-TSSOP
Package / Case [x]0.173 in
Package / Case [y]4.4 mm
Supplier Device Package20-TSSOP
Voltage - Supply [Max]6 V
Voltage - Supply [Min]2 V

SN74HC373A Series

High Speed CMOS Logic Octal Transparent Latches with 3-State Outputs

PartCurrent - Output High, Low [custom]Current - Output High, Low [custom]Supplier Device PackageOperating Temperature [Min]Operating Temperature [Max]Independent CircuitsOutput TypeDelay Time - PropagationVoltage - Supply [Min]Voltage - Supply [Max]Logic TypePackage / CasePackage / Case [y]Package / Case [y]Mounting TypeCircuit [custom]Circuit [custom]Package / CasePackage / CasePackage / Case [x]
Product Image
Texas Instruments
7.8 mA
7.8 mA
20-SOIC
-55 °C
125 °C
1
Tri-State
30 ns
2 V
6 V
D-Type Transparent Latch
20-SOIC
0.295 in
7.5 mm
Surface Mount
8
8
20 TSSOP
Texas Instruments
7.8 mA
7.8 mA
20-SO
-40 °C
85 °C
1
Tri-State
15 ns
2 V
6 V
D-Type Transparent Latch
20-SOIC
Surface Mount
8
8
0.209 "
5.3 mm
20-DIP
Texas Instruments
7.8 mA
7.8 mA
20-PDIP
-40 °C
85 °C
1
Tri-State
15 ns
2 V
6 V
D-Type Transparent Latch
20-DIP
Through Hole
8
8
0.3 in
7.62 mm
20-SSOP
Texas Instruments
7.8 mA
7.8 mA
20-SSOP
-40 °C
85 °C
1
Tri-State
15 ns
2 V
6 V
D-Type Transparent Latch
20-SSOP
Surface Mount
8
8
20-pin (PW) package image
Texas Instruments
7.8 mA
7.8 mA
20-TSSOP
-40 °C
85 °C
1
Tri-State
15 ns
2 V
6 V
D-Type Transparent Latch
20-TSSOP
4.4 mm
Surface Mount
8
8
0.173 in
20-TSSOP
Texas Instruments
7.8 mA
7.8 mA
20-TSSOP
-40 °C
85 °C
1
Tri-State
15 ns
2 V
6 V
D-Type Transparent Latch
20-TSSOP
4.4 mm
Surface Mount
8
8
0.173 in
20-SOIC Pkg
Texas Instruments
7.8 mA
7.8 mA
20-SOIC
-55 °C
125 °C
1
Tri-State
30 ns
2 V
6 V
D-Type Transparent Latch
20-SOIC
0.295 in
7.5 mm
Surface Mount
8
8
20-SOIC,DW
Texas Instruments
7.8 mA
7.8 mA
20-SOIC
-40 °C
85 °C
1
Tri-State
15 ns
2 V
6 V
D-Type Transparent Latch
20-SOIC
0.295 in
7.5 mm
Surface Mount
8
8
INA4181A3QPWRQ1
Texas Instruments
7.8 mA
7.8 mA
20-TSSOP
-40 °C
85 °C
1
Tri-State
15 ns
2 V
6 V
D-Type Transparent Latch
20-TSSOP
4.4 mm
Surface Mount
8
8
0.173 in
20-TSSOP
Texas Instruments
7.8 mA
7.8 mA
20-TSSOP
-40 °C
85 °C
1
Tri-State
15 ns
2 V
6 V
D-Type Transparent Latch
20-TSSOP
4.4 mm
Surface Mount
8
8
0.173 in

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 1.26
10$ 1.13
70$ 1.07
140$ 0.88
280$ 0.82
Texas InstrumentsTUBE 1$ 0.93
100$ 0.72
250$ 0.53
1000$ 0.38

Description

General part information

SN74HC373A Series

This 8-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the SN74HC373A are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that were set up at the D inputs.

An output-enable (OE\) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.