Integrated Circuits (ICs)

SN74HC373NS

Obsolete

Texas Instruments

IC D-TYPE TRANSP SGL 8:8 20SO

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DocumentsDatasheet

Integrated Circuits (ICs)

SN74HC373NS

Obsolete

Texas Instruments

IC D-TYPE TRANSP SGL 8:8 20SO

Deep-Dive with AI

DocumentsDatasheet

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	SN74HC373NS

Circuit [custom]	8
Circuit [custom]	8
Current - Output High, Low [custom]	7.8 mA
Current - Output High, Low [custom]	7.8 mA
Delay Time - Propagation	15 ns
Independent Circuits	1
Logic Type	D-Type Transparent Latch
Mounting Type	Surface Mount
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	Tri-State
Package / Case	20-SOIC
Package / Case	0.209 "
Package / Case	5.3 mm
Supplier Device Package	20-SO
Voltage - Supply [Max]	6 V
Voltage - Supply [Min]	2 V

SN74HC373A Series

High Speed CMOS Logic Octal Transparent Latches with 3-State Outputs

Part	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Supplier Device Package	Operating Temperature [Min]	Operating Temperature [Max]	Independent Circuits	Output Type	Delay Time - Propagation	Voltage - Supply [Min]	Voltage - Supply [Max]	Logic Type	Package / Case	Package / Case [y]	Package / Case [y]	Mounting Type	Circuit [custom]	Circuit [custom]	Package / Case	Package / Case	Package / Case [x]
Texas Instruments CD74HC373M96	7.8 mA	7.8 mA	20-SOIC	-55 °C	125 °C	1	Tri-State	30 ns	2 V	6 V	D-Type Transparent Latch	20-SOIC	0.295 in	7.5 mm	Surface Mount	8	8
Texas Instruments SN74HC373NS	7.8 mA	7.8 mA	20-SO	-40 °C	85 °C	1	Tri-State	15 ns	2 V	6 V	D-Type Transparent Latch	20-SOIC			Surface Mount	8	8	0.209 "	5.3 mm
Texas Instruments SN74HC373N	7.8 mA	7.8 mA	20-PDIP	-40 °C	85 °C	1	Tri-State	15 ns	2 V	6 V	D-Type Transparent Latch	20-DIP			Through Hole	8	8	0.3 in	7.62 mm
Texas Instruments SN74HC373DBR	7.8 mA	7.8 mA	20-SSOP	-40 °C	85 °C	1	Tri-State	15 ns	2 V	6 V	D-Type Transparent Latch	20-SSOP			Surface Mount	8	8
Texas Instruments SN74HC373PW	7.8 mA	7.8 mA	20-TSSOP	-40 °C	85 °C	1	Tri-State	15 ns	2 V	6 V	D-Type Transparent Latch	20-TSSOP	4.4 mm		Surface Mount	8	8			0.173 in
Texas Instruments SN74HC373PWRG4	7.8 mA	7.8 mA	20-TSSOP	-40 °C	85 °C	1	Tri-State	15 ns	2 V	6 V	D-Type Transparent Latch	20-TSSOP	4.4 mm		Surface Mount	8	8			0.173 in
Texas Instruments CD74HC373M	7.8 mA	7.8 mA	20-SOIC	-55 °C	125 °C	1	Tri-State	30 ns	2 V	6 V	D-Type Transparent Latch	20-SOIC	0.295 in	7.5 mm	Surface Mount	8	8
Texas Instruments SN74HC373DW	7.8 mA	7.8 mA	20-SOIC	-40 °C	85 °C	1	Tri-State	15 ns	2 V	6 V	D-Type Transparent Latch	20-SOIC	0.295 in	7.5 mm	Surface Mount	8	8
Texas Instruments SN74HC373PWT	7.8 mA	7.8 mA	20-TSSOP	-40 °C	85 °C	1	Tri-State	15 ns	2 V	6 V	D-Type Transparent Latch	20-TSSOP	4.4 mm		Surface Mount	8	8			0.173 in
Texas Instruments SN74HC373PWRE4	7.8 mA	7.8 mA	20-TSSOP	-40 °C	85 °C	1	Tri-State	15 ns	2 V	6 V	D-Type Transparent Latch	20-TSSOP	4.4 mm		Surface Mount	8	8			0.173 in

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tube	1	$ 1.32
		10	$ 1.18
		40	$ 1.12
		120	$ 0.92
		280	$ 0.86
		520	$ 0.76
		1000	$ 0.60

Description

General part information

SN74HC373A Series

This 8-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the SN74HC373A are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that were set up at the D inputs.

An output-enable (OE\) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

Documents

Technical documentation and resources