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74HC175PW-Q100J
Integrated Circuits (ICs)

74HC175PW-Q100J

Active
Nexperia USA Inc.

FLIP FLOP D-TYPE BUS INTERFACE POS-EDGE 1-ELEMENT 16-PIN TSSOP T/R AUTOMOTIVE AEC-Q100

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74HC175PW-Q100J
Integrated Circuits (ICs)

74HC175PW-Q100J

Active
Nexperia USA Inc.

FLIP FLOP D-TYPE BUS INTERFACE POS-EDGE 1-ELEMENT 16-PIN TSSOP T/R AUTOMOTIVE AEC-Q100

Technical Specifications

Parameters and characteristics for this part

Specification74HC175PW-Q100J
Clock Frequency89 MHz
Current - Output High, Low [custom]5.2 mA
Current - Output High, Low [custom]5.2 mA
Current - Quiescent (Iq)8 ÁA
GradeAutomotive
Input Capacitance3.5 pF
Max Propagation Delay @ V, Max CL30 ns
Mounting TypeSurface Mount
Number of Bits per Element4
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Output TypeComplementary
Package / Case16-TSSOP
Package / Case [y]4.4 mm
Package / Case [y]0.173 in
QualificationAEC-Q100
Supplier Device Package16-TSSOP
Trigger TypePositive Edge
TypeD-Type
Voltage - Supply [Max]6 V
Voltage - Supply [Min]2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyBulk 1504$ 0.20
N/A 2416$ 0.76
4899$ 0.39

Description

General part information

74HC175PW-Q100 Series

The 74HC175-Q100; 74HCT175-Q100 are quad positive edge-triggered D-type flip-flops with individual data inputs (Dn) and both Qn andQn outputs. The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW onMRcauses the flip-flops and outputs to be reset LOW.