74HC175PW-Q100 Series

Quad D-type flip-flop with reset; positive-edge trigger

Catalog

Quad D-type flip-flop with reset; positive-edge trigger

Part	Supplier Device Package	Package / Case [y]	Package / Case	Package / Case [y]	Clock Frequency	Current - Quiescent (Iq)	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Output Type	Operating Temperature [Max]	Operating Temperature [Min]	Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Mounting Type	Grade	Number of Bits per Element	Qualification	Trigger Type	Max Propagation Delay @ V, Max CL	Number of Elements	Input Capacitance
Nexperia USA Inc. 74HC175PW-Q100J	16-TSSOP	4.4 mm	16-TSSOP	0.173 in	89 MHz	8 ÁA	5.2 mA	5.2 mA	Complementary	125 °C	-40 °C	D-Type	6 V	2 V	Surface Mount	Automotive	4	AEC-Q100	Positive Edge	30 ns	1	3.5 pF

Catalog

Quad D-type flip-flop with reset; positive-edge trigger

Description

The 74HC175-Q100; 74HCT175-Q100 are quad positive edge-triggered D-type flip-flops with individual data inputs (Dn) and both Qn andQn outputs. The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW onMRcauses the flip-flops and outputs to be reset LOW.