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16 QFN
Integrated Circuits (ICs)

MD1812K6-G

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Microchip Technology

HIGH SPEED QUAD MOSFET DRIVER 16 QFN 4X4X0.9MM T/R ROHS COMPLIANT: YES

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16 QFN
Integrated Circuits (ICs)

MD1812K6-G

Active
Microchip Technology

HIGH SPEED QUAD MOSFET DRIVER 16 QFN 4X4X0.9MM T/R ROHS COMPLIANT: YES

Technical Specifications

Parameters and characteristics for this part

SpecificationMD1812K6-G
Channel TypeIndependent
Current - Peak Output (Source, Sink) [custom]2 A
Current - Peak Output (Source, Sink) [custom]2 A
Driven ConfigurationHalf-Bridge
Gate TypeN-Channel, P-Channel MOSFET
Input TypeInverting
Logic Voltage - VIL, VIH1.7 V, 0.3 V
Mounting TypeSurface Mount
Number of Drivers4
Operating Temperature [Max]125 °C
Operating Temperature [Min]-25 °C
Package / Case16-VQFN Exposed Pad
Rise / Fall Time (Typ) [custom]6 ns
Rise / Fall Time (Typ) [custom]6 ns
Supplier Device Package16-QFN (4x4)
Voltage - Supply [Max]13 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTape & Reel (TR) 3300$ 2.98
Microchip DirectT/R 1$ 3.69
25$ 3.06
100$ 2.79
1000$ 2.69
5000$ 2.65
NewarkEach (Supplied on Full Reel) 100$ 1.73

Description

General part information

MD1812 Series

MD1812 is a high-speed quad MOSFET driver. It is designed to drive two N and two P-channel high voltage DMOS FETs for medical ultrasound applications, but may be used in any application that needs a high output current for a capacitive load. The input stage of the MD1812 is a high-speed level translator that is able to operate from logic input signals of 1.8 to 5.0V amplitude. An adaptive threshold circuit is used to set the level translator threshold to the average of the input logic 0 and logic 1 levels. The level translator uses a proprietary circuit which provides DC coupling together with high-speed operation. The output stage of the MD1812 has separate power connections enabling the output signal L and H levels to be chosen independently from the driver supply voltages.

As an example, the input logic levels may be 0V and 1.8V, the control logic may be powered by +5V and –5V, and the output L and H levels may be varied anywhere over the range of -5.0 to +5.0V. The output stage is capable of peak currents of up to ±2.0 amps depending on the supply voltages used and load capacitance. The OE pin serves a dual purpose. First, its logic H level is used to compute the threshold voltage level for the channel input level translators. Secondly, when OE is low, the outputs are disabled, with the A and C outputs high and the B and D outputs low. This assists in properly pre-charging the coupling capacitors that may be used in series in the gate drive circuit of an external PMOS and NMOS. A built-in level shifter provides PMOS gate negative bias drive. This enables the user-defined damping control to generate return-to-zero bipolar output pulses.