STM32WB15CCU6
ActiveULTRA-LOW-POWER DUAL CORE ARM CORTEX-M4 MCU 64 MHZ, CORTEX-M0+ 32 MHZ WITH 320 KBYTES OF FLASH MEMORY, BLUETOOTH LE 5.3, AES-256
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STM32WB15CCU6
ActiveULTRA-LOW-POWER DUAL CORE ARM CORTEX-M4 MCU 64 MHZ, CORTEX-M0+ 32 MHZ WITH 320 KBYTES OF FLASH MEMORY, BLUETOOTH LE 5.3, AES-256
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Technical Specifications
Parameters and characteristics for this part
| Specification | STM32WB15CCU6 |
|---|---|
| Current - Receiving [Max] | 7.7 mA |
| Current - Receiving [Min] | 4.5 mA |
| Current - Transmitting [Max] [x] | 12.5 mA |
| Current - Transmitting [Min] [x] | 5.2 mA |
| Data Rate (Max) [Max] | 2 Mbps |
| Frequency | 2.4 GHz |
| GPIO | 30 |
| Memory Size | 320 kB, 48 kB |
| Modulation | GFSK |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 105 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 48-UFQFN Exposed Pad |
| Power - Output | 5.5 dBm |
| Protocol | Bluetooth v5.2 |
| RF Family/Standard | Bluetooth |
| Sensitivity | -95.5 dBm |
| Serial Interfaces | UART, SPI, USART, ADC, I2C |
| Supplier Device Package | 48-UFQFPN (7x7) |
| Type | TxRx + MCU |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 1.71 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | N/A | 1598 | $ 4.75 | |
Description
General part information
STM32WB15CC Series
The STM32WB15CC multiprotocol wireless and ultra-low-power device embeds a powerful and ultra-low-power radio compliant with the Bluetooth®Low Energy SIG specification 5.4. It contains a dedicated Arm®Cortex®-M0+ for performing all the real-time low layer operation.
The device is designed to be extremely low-power and is based on the high-performance Arm®Cortex®-M4 32-bit RISC core operating at a frequency of up to 64 MHz. This core features a Floating point unit (FPU) single precision that supports all Arm®single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) that enhances application security.
Enhanced inter-processor communication is provided by the IPCC with six bidirectional channels. The HSEM provides hardware semaphores used to share common resources between the two processors.
Documents
Technical documentation and resources
