Specification	V62/05621-01XE

Clock Frequency	160 MHz
Current - Output High, Low [x]	32 mA
Current - Output High, Low [y]	32 mA
Current - Quiescent (Iq)	10 µA
Function	Standard
Input Capacitance	4 pF
Max Propagation Delay @ V, Max CL	4.5 ns
Mounting Type	Surface Mount
Number of Bits per Element	1
Number of Elements	1
Operating Temperature [Max]	115 °C
Operating Temperature [Min]	-55 C
Output Type	Non-Inverted
Package / Case	SC-70-5, 5-TSSOP, SOT-353
Supplier Device Package	SC-70-5
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	1.65 V

SN74LVC1G79-EP Series

Enhanced Product Single Positive-Edge-Triggered D-Type Flip-Flop

Part	Trigger Type	Package / Case	Operating Temperature [Min]	Operating Temperature [Max]	Type	Number of Elements	Output Type	Supplier Device Package	Max Propagation Delay @ V, Max CL	Current - Quiescent (Iq)	Clock Frequency	Current - Output High, Low [y]	Current - Output High, Low [x]	Function	Input Capacitance	Number of Bits per Element	Voltage - Supply [Max]	Voltage - Supply [Min]	Mounting Type
Texas Instruments V62/05621-01XE	Positive Edge	5-TSSOP SC-70-5 SOT-353	-55 C	115 °C	D-Type	1	Non-Inverted	SC-70-5	4.5 ns	10 µA	160 MHz	32 mA	32 mA	Standard	4 pF	1	5.5 V	1.65 V	Surface Mount

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tape & Reel (TR)	3000	$ 0.81
Texas Instruments	LARGE T&R	1	$ 1.60
		100	$ 1.23
		250	$ 0.91
		1000	$ 0.65

Description

General part information

SN74LVC1G79-EP Series

This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation.

When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output.

This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Documents

Technical documentation and resources

LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)

V62/05621-01XE

Deep-Dive with AI

V62/05621-01XE

Deep-Dive with AI

Technical Specifications

SN74LVC1G79-EP Series

Pricing

Description

SN74LVC1G79-EP Series

Documents

LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)

LOGIC Pocket Data Book (Rev. B)

Live Insertion

Understanding Advanced Bus-Interface Products Design Guide

SN74LVC1G79-EP datasheet (Rev. A)

STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS

Use of the CMOS Unbuffered Inverter in Oscillator Circuits

Implications of Slow or Floating CMOS Inputs (Rev. E)

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Signal Switch Data Book (Rev. A)

Logic Guide (Rev. AB)

Selecting the Right Level Translation Solution (Rev. A)

CMOS Power Consumption and CPD Calculation (Rev. B)

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Design Summary for WCSP Little Logic (Rev. B)

TI IBIS File Creation, Validation, and Distribution Processes

Low-Voltage Logic (LVC) Designer's Guide

Texas Instruments Little Logic Application Report

How to Select Little Logic (Rev. A)

LVC Characterization Information

Input and Output Characteristics of Digital Integrated Circuits

Little Logic Guide 2018 (Rev. G)

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Standard Linear & Logic for PCs, Servers & Motherboards

Power-Up Behavior of Clocked Devices (Rev. B)

SN74LVC1G79-EP Series