
SN74LVC1G79-EP Series
Enhanced Product Single Positive-Edge-Triggered D-Type Flip-Flop
Manufacturer: Texas Instruments
Catalog
Enhanced Product Single Positive-Edge-Triggered D-Type Flip-Flop
Key Features
• Supports 5-V VCCOperationInputs Accept Voltages to 5.5 VMax tpdof 5 ns at 3.3 VLow Power Consumption, 10-µA Max ICC±24-mA Output Drive at 3.3 VIoffSupports Partial-Power-Down Mode OperationLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONSControlled BaselineOne Assembly/Test SiteOne Fabrication SiteAvailable in Military (–55°C/125°C) Temperature Range(1)Extended Product Life CycleExtended Product-Change NotificationProduct Traceability(1)Additional temperature ranges are available - contact factory.Supports 5-V VCCOperationInputs Accept Voltages to 5.5 VMax tpdof 5 ns at 3.3 VLow Power Consumption, 10-µA Max ICC±24-mA Output Drive at 3.3 VIoffSupports Partial-Power-Down Mode OperationLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONSControlled BaselineOne Assembly/Test SiteOne Fabrication SiteAvailable in Military (–55°C/125°C) Temperature Range(1)Extended Product Life CycleExtended Product-Change NotificationProduct Traceability(1)Additional temperature ranges are available - contact factory.
Description
AI
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation.
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation.
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.