Zenode.ai Logo
Beta
AM6852ATGGHAALZR
Integrated Circuits (ICs)

AM6852ATGGHAALZR

Active
Texas Instruments

GENERAL PURPOSE SOC WITH DUAL CORE 64-BIT ARM CORTEX-A72, GRAPHICS, 1-PORT PCIE GEN3, USB3.0

Deep-Dive with AI

Search across all available documentation for this part.

AM6852ATGGHAALZR
Integrated Circuits (ICs)

AM6852ATGGHAALZR

Active
Texas Instruments

GENERAL PURPOSE SOC WITH DUAL CORE 64-BIT ARM CORTEX-A72, GRAPHICS, 1-PORT PCIE GEN3, USB3.0

Technical Specifications

Parameters and characteristics for this part

SpecificationAM6852ATGGHAALZR
Additional InterfacesGPIO, I2C, SPI, QSPI, CANbus, UART/USART, PCIe, DMA, MMC/SD
Co-Processors/DSPARM® Cortex®-R5F, Multimedia, GPU
Core ProcessorARM® Cortex®-A72
Display & Interface ControllerseDP, MIPI-DSI, DPI
Ethernet10 Mbps, 1000 Mbps, 100 Mbps
Ethernet2
Graphics AccelerationTrue
Mounting TypeSurface Mount
Number of Cores/Bus Width64 Bit, 2 Core
Operating Temperature [custom]-40 °C, 105 °C
Package / Case770-BFBGA, FCBGA
RAM ControllersLPDDR4
Security FeaturesMD5, SHA, SMS, AES, ECC, 3DES, DRBG, Random Number Generator, Cryptography, RSA, Secure Boot, PKA
Speed2 GHz
Supplier Device Package770-FCBGA (23x23)
USBUSB 3.1 (1)
Voltage - I/O1.1 V, 1.8 V, 3.3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTape & Reel (TR) 250$ 73.23
Texas InstrumentsLARGE T&R 1$ 85.34
100$ 75.86
250$ 62.36
1000$ 55.78

Description

General part information

AM68 Series

The AM68 scalable processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera and General Compute applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The AM68x family is built for a broad set of cost-sensitive high-performance compute applications in Factory Automation, Building Automation, and other markets.

The AM68 provides high performance compute technology for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include the latest Arm and GPU processors for general compute, next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, an integrated next generation imaging subsystem (ISP), video codec, and isolated MCU island. All protected by industrial-grade safety and security hardware accelerators.

General Compute Cores and Integration Overview: Separate dual core cluster configuration of Arm® Cortex®-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Up to two Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72 core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to SIL-2 levels while the integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs.

Documents

Technical documentation and resources

Datasheet

Datasheet

Designing an Efficient Edge AI System with Highly Integrated Processors (Rev. A)

White paper

How to simplify your embedded edge AI application development

Technical article

TÜV SÜD Certificate for Functional Safety Software Development Process (Rev. C)

Functional safety information

Using TSN Ethernet Features to Improve Timing in Industrial Ethernet Controllers

Application note

OSPI Tuning Procedure

Application note

SK-AM68 Process Starter Kit User's Guide

User guide

Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design Guidelines (Rev. A)

Application note

J721E, J721S2, J7200, J784S4 MCAL TUV Certification

Functional safety information

고도로 통합된 프로세서를 사용해 효 율적인 에지 AI 시스템 설계 (Rev. A)

White paper

MMC SW Tuning Algorithm (Rev. A)

Application note

Jacinto7 DDRSS Register Configuration Tool (Rev. B)

Application note

Top Five Design Considerations for Smart Multi-display Systems

Application brief

智慧多顯示器系統的五個主要設計考量

Application brief

Enabling MAC2MAC Feature on Jacinto7 Soc

Application note

AM68x Processor Power Solutions Using LP87334E PMIC for Industrial Applications

Application note

Debugging GPU Driver Issues on TDA4x and AM6x Devices

Application note

UART Log Debug System on Jacinto 7 SoC

Application note

Jacinto7 AM6x/TDA4x/DRA8x Schematic Checklist (Rev. B)

Application note

Sicherheitsaktivierung auf Jacinto™ 7-Prozessoren

White paper

Securing Arm-Based Application Processors (Rev. F)

White paper

SPI Enablement & Validation on TDA4 Family

Application note

Security Enablers on Jacinto™ 7 Processors

White paper

General Purpose processors for high compute, graphics, and connectivity applications

White paper

Jacinto™ 7 프로세서의 MCU 통합으로 차별화 지원

White paper

AM68 Power Estimation Tool User’s Guide (Rev. A)

User guide

스마트 다중 디스플레이 시스템을 위한 5가지 설계 고려 사항

Application brief

Jacinto7 HS Device Customer Return Process

Application note

以高度整合處理器設計高效邊緣 AI 系統 (Rev. A)

White paper

J721S2, TDA4VE, TDA4AL, TDA4VL, AM68A Processor Silicon Errata (Rev. C)

Errata

Jacinto 7 LPDDR4 Board Design and Layout Guidelines (Rev. F)

Application note

Differenzierungsmöglichkeit durch MCU-Integration Prozessoren der Reihe Jacinto™

White paper

J721S2/TDA4VE/TDA4VL/TDA4AL EVM User Guide

User guide

Enabling Differentiation through MCU Integration on Jacinto™ 7 Processors

White paper

Jacinto™ 7 프로세서의 보안 구현 도구

White paper

TDA4 Flashing Techniques

Application note

Dual-TDA4x System Solution

Application note