AM68 Series

General Purpose SoC with dual core 64-bit Arm Cortex-A72, graphics, 1-port PCIe Gen3, USB3.0

Catalog

General Purpose SoC with dual core 64-bit Arm Cortex-A72, graphics, 1-port PCIe Gen3, USB3.0

Part	Graphics Acceleration	Supplier Device Package	Number of Cores/Bus Width	Voltage - I/O	Core Processor	Security Features	Operating Temperature [custom]	USB	Mounting Type	Speed	Additional Interfaces	Package / Case	Display & Interface Controllers	RAM Controllers	Ethernet	Ethernet	Co-Processors/DSP
Texas Instruments AM6852ATGGHAALZR		770-FCBGA (23x23)	2 Core 64 Bit	1.1 V 1.8 V 3.3 V	ARM® Cortex®-A72	3DES AES Cryptography DRBG ECC MD5 PKA Random Number Generator RSA Secure Boot SHA SMS	-40 °C 105 °C	USB 3.1 (1)	Surface Mount	2 GHz	CANbus DMA GPIO I2C MMC/SD PCIe QSPI SPI UART/USART	770-BFBGA FCBGA	DPI eDP MIPI-DSI	LPDDR4	10 Mbps 100 Mbps 1000 Mbps	2	ARM® Cortex®-R5F Multimedia GPU

Catalog

General Purpose SoC with dual core 64-bit Arm Cortex-A72, graphics, 1-port PCIe Gen3, USB3.0

Key Features

• Processor cores:Up to dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2GHz1MB shared L2 cache per dual-core Cortex-A72 cluster32KB L1 D-Cache and 48KB L1 I-Cache per Cortex-A72 coreDeep Learning Accelerator:Up to 8 Trillion Operations Per Second (TOPS)Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist acceleratorsDual-core Arm Cortex-R5F MCUs at up to 1.0GHz in General Compute partition with FFI16KB L1 D-Cache, 16KB L1 I-Cache, and 64KB L2 TCMDual-core Arm® Cortex®-R5F MCUs at up to 1.0 GHz to support Device Management32K L1 D-Cache, 32K I-Cache, and 64K L2 TCM with SECDED ECC on all memoriesVision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators480 MPixel/s ISPSupport for up to 16-bit input RAW formatWide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) supportOutput color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSLMultimedia:Display subsystem supports:Up to 4 displaysUp to two DSI 4L TX (up to 2.5K)One eDP 4LOne DPI 24-bit RGB parallel interfaceSafety features such as freeze frame detection and MISR data check3D Graphics Processing UnitIMG BXS-4-64, up to 800MHz50GFLOPS, 4GTexels/s>500MTexels/s, >8GFLOPsSupports at least 2 composition layersSupports up to 2048x1080 @60fpsSupports ARGB32, RGB565 and YUV formats2D graphics capableOpenGL ES 3.1, Vulkan 1.2Two CSI2.0 4L Camera Serial interface (CSI-Rx) Plus CSI2.- 4L Tx (CSI-Tx) with DPHYMIPI CSI 1.3 Compliant + MIPI-DPHY 1.2Support for 1,2,3, or 4 data lane mode up to 2.5GbpsECC verification/correction with CRC check + ECC on RAMVirtual Channel support (up to 16)Ability to write stream data directly to DDR via DMAVideo Encoder/DecoderSupport for HEVC (H.265) Main profiles at Level 5.1 High-tierSupport for H.264 BaseLine/Main/High Profiles at Level 5.2Support for up to 4K UHD resolution (3840 × 2160)4K60 H.264/H.265 Encode/Decode (up to 480MP/s)Memory subsystem:Up to 4MB of on-chip L3 RAM with ECC and coherencyECC error protectionShared coherent cacheSupports internal DMA engineUp to two External Memory Interface (EMIF) modules with ECCSupports LPDDR4 memory typesSupports speeds up to 4266MT/sUp to two 32-bit data bus with inline ECC up to 17GB/s per EMIFGeneral-Purpose Memory Controller (GPMC)Up to two 512KB on-chip SRAM in MAIN domain, protected by ECCDevice security:Secure boot with secure run-time supportCustomer programmable root key, up to RSA-4K or ECC-512Embedded hardware security moduleCrypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DESHigh speed serial interfaces:One PCI-Express (PCIe) Gen3 controllersUp to four lanes per controllerGen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiationOne USB 3.0 dual-role device (DRD) subsystemEnhanced SuperSpeed Gen1 PortSupports Type-C switchingIndependently configurable as USB host, USB peripheral, or USB DRDTwo CSI2.0 4L Camera Serial interface RX (CSI-RX) plus two CSI2.0 4L TX (CSI-TX) with DPHYMIPI CSI 1.3 Compliant + MIPI-DPHY 1.2CSI-RX supports for 1,2,3, or 4 data lane mode up to 2.5Gbps per laneCSI-TX supports for 1,2, or 4 data lane mode up to 2.5Gbps per laneEthernet:Two Ethernet RMII/RGMII interfacesFlash memory interfaces:Embedded MultiMediaCard Interface (eMMC™ 5.1)One Secure Digital 3.0/Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0)Two simultaneous flash interfaces configured asOne OSPI or HyperBus™ or QSPI, andOne QSPITechnology / Package:16-nm FinFET technology23mm x 23mm, 0.8-mm pitch, 770-pin FCBGA (ALZ)Processor cores:Up to dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2GHz1MB shared L2 cache per dual-core Cortex-A72 cluster32KB L1 D-Cache and 48KB L1 I-Cache per Cortex-A72 coreDeep Learning Accelerator:Up to 8 Trillion Operations Per Second (TOPS)Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist acceleratorsDual-core Arm Cortex-R5F MCUs at up to 1.0GHz in General Compute partition with FFI16KB L1 D-Cache, 16KB L1 I-Cache, and 64KB L2 TCMDual-core Arm® Cortex®-R5F MCUs at up to 1.0 GHz to support Device Management32K L1 D-Cache, 32K I-Cache, and 64K L2 TCM with SECDED ECC on all memoriesVision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators480 MPixel/s ISPSupport for up to 16-bit input RAW formatWide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) supportOutput color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSLMultimedia:Display subsystem supports:Up to 4 displaysUp to two DSI 4L TX (up to 2.5K)One eDP 4LOne DPI 24-bit RGB parallel interfaceSafety features such as freeze frame detection and MISR data check3D Graphics Processing UnitIMG BXS-4-64, up to 800MHz50GFLOPS, 4GTexels/s>500MTexels/s, >8GFLOPsSupports at least 2 composition layersSupports up to 2048x1080 @60fpsSupports ARGB32, RGB565 and YUV formats2D graphics capableOpenGL ES 3.1, Vulkan 1.2Two CSI2.0 4L Camera Serial interface (CSI-Rx) Plus CSI2.- 4L Tx (CSI-Tx) with DPHYMIPI CSI 1.3 Compliant + MIPI-DPHY 1.2Support for 1,2,3, or 4 data lane mode up to 2.5GbpsECC verification/correction with CRC check + ECC on RAMVirtual Channel support (up to 16)Ability to write stream data directly to DDR via DMAVideo Encoder/DecoderSupport for HEVC (H.265) Main profiles at Level 5.1 High-tierSupport for H.264 BaseLine/Main/High Profiles at Level 5.2Support for up to 4K UHD resolution (3840 × 2160)4K60 H.264/H.265 Encode/Decode (up to 480MP/s)Memory subsystem:Up to 4MB of on-chip L3 RAM with ECC and coherencyECC error protectionShared coherent cacheSupports internal DMA engineUp to two External Memory Interface (EMIF) modules with ECCSupports LPDDR4 memory typesSupports speeds up to 4266MT/sUp to two 32-bit data bus with inline ECC up to 17GB/s per EMIFGeneral-Purpose Memory Controller (GPMC)Up to two 512KB on-chip SRAM in MAIN domain, protected by ECCDevice security:Secure boot with secure run-time supportCustomer programmable root key, up to RSA-4K or ECC-512Embedded hardware security moduleCrypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DESHigh speed serial interfaces:One PCI-Express (PCIe) Gen3 controllersUp to four lanes per controllerGen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiationOne USB 3.0 dual-role device (DRD) subsystemEnhanced SuperSpeed Gen1 PortSupports Type-C switchingIndependently configurable as USB host, USB peripheral, or USB DRDTwo CSI2.0 4L Camera Serial interface RX (CSI-RX) plus two CSI2.0 4L TX (CSI-TX) with DPHYMIPI CSI 1.3 Compliant + MIPI-DPHY 1.2CSI-RX supports for 1,2,3, or 4 data lane mode up to 2.5Gbps per laneCSI-TX supports for 1,2, or 4 data lane mode up to 2.5Gbps per laneEthernet:Two Ethernet RMII/RGMII interfacesFlash memory interfaces:Embedded MultiMediaCard Interface (eMMC™ 5.1)One Secure Digital 3.0/Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0)Two simultaneous flash interfaces configured asOne OSPI or HyperBus™ or QSPI, andOne QSPITechnology / Package:16-nm FinFET technology23mm x 23mm, 0.8-mm pitch, 770-pin FCBGA (ALZ)

Description

The AM68 scalable processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera and General Compute applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The AM68x family is built for a broad set of cost-sensitive high-performance compute applications in Factory Automation, Building Automation, and other markets. The AM68 provides high performance compute technology for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include the latest Arm and GPU processors for general compute, next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, an integrated next generation imaging subsystem (ISP), video codec, and isolated MCU island. All protected by industrial-grade safety and security hardware accelerators. General Compute Cores and Integration Overview: Separate dual core cluster configuration of Arm® Cortex®-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Up to two Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72 core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to SIL-2 levels while the integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs. Key Performance Cores Overview: The C7000™ DSP next generation core ("C7x") combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating-point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. The new "MMA" deep learning accelerator enables performance up to 8 Trillion Operations Per Second (TOPS) within the lowest power envelope in the industry even when operating even at the worst case junction temperatures of 105°C and 125°C. The dedicated Vision hardware accelerators provide vision pre-processing with no impact on system performance. The C7x/MMA cores are available only for deep learning function in the AM68 class of processors. The AM68 scalable processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera and General Compute applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The AM68x family is built for a broad set of cost-sensitive high-performance compute applications in Factory Automation, Building Automation, and other markets. The AM68 provides high performance compute technology for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include the latest Arm and GPU processors for general compute, next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, an integrated next generation imaging subsystem (ISP), video codec, and isolated MCU island. All protected by industrial-grade safety and security hardware accelerators. General Compute Cores and Integration Overview: Separate dual core cluster configuration of Arm® Cortex®-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Up to two Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72 core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to SIL-2 levels while the integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs. Key Performance Cores Overview: The C7000™ DSP next generation core ("C7x") combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating-point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. The new "MMA" deep learning accelerator enables performance up to 8 Trillion Operations Per Second (TOPS) within the lowest power envelope in the industry even when operating even at the worst case junction temperatures of 105°C and 125°C. The dedicated Vision hardware accelerators provide vision pre-processing with no impact on system performance. The C7x/MMA cores are available only for deep learning function in the AM68 class of processors.