
AD9691BCPZRL7-1250
Active1-CHANNEL DUAL ADC PIPELINED 1.25GSPS 14-BIT JESD204B 88-PIN LFCSP EP T/R
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AD9691BCPZRL7-1250
Active1-CHANNEL DUAL ADC PIPELINED 1.25GSPS 14-BIT JESD204B 88-PIN LFCSP EP T/R
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Technical Specifications
Parameters and characteristics for this part
| Specification | AD9691BCPZRL7-1250 |
|---|---|
| Architecture | Pipelined |
| Configuration | S/H-ADC |
| Data Interface | JESD204B |
| Features | Simultaneous Sampling |
| Input Type | Differential |
| Mounting Type | Surface Mount |
| Number of A/D Converters | 1 |
| Number of Bits | 14 |
| Number of Inputs | 2 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 88-VFQFN Exposed Pad, CSP |
| Ratio - S/H:ADC | 1:1 |
| Reference Type | Internal |
| Sampling Rate (Per Second) | 1.25 G |
| Supplier Device Package | 88-LFCSP-VQ (12x12) |
| Voltage - Supply, Analog [Max] | 1.28 V, 2.56 V |
| Voltage - Supply, Analog [Min] | 2.44 V, 1.22 V |
| Voltage - Supply, Digital [Max] | 1.28 V |
| Voltage - Supply, Digital [Min] | 1.22 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tape & Reel (TR) | 400 | $ 998.27 | |
Description
General part information
AD9691 Series
The AD9691 is a dual, 14-bit, 1.25 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. The device is designed for sampling wide bandwidth analog signals of up to 1.5 GHz.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.Each ADC data output is internally connected to two digital downconverters (DDCs). Each DDC consists of four cascaded signal processing stages: a 12-bit frequency translator (NCO) and four half-band decimation filters.In addition to the DDC blocks, the AD9691 has a programmable threshold detector that allows monitoring of the incoming signal power using the fast detect output bits of the ADC. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, four- or eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF± input pins.The AD9691 is available in a Pb-free, 88-lead LFCSP and is specified over the −40°C to +85°C industrial temperature range. This product is protected by a U.S. patent.Product HighlightsLow power consumption analog core, 14-bit, 1.25 GSPS dual analog-to-digital converter (ADC) with 1.9 W per channel.Wide full power bandwidth supports IF sampling of signals up to 1.5 GHz.Buffered inputs with programmable input termination eases filter design and implementation.Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements.Programmable fast overrange detection.12 mm × 12 mm 88-lead LFCSP.ApplicationsCommunications (wideband receivers and digital predistortion)Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions)DOCSIS 3.x CMTS upstream receive pathsHigh speed data acquisition systems
Documents
Technical documentation and resources